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Committee Date Time Place Paper Title / Authors Abstract Paper #
SS, MSS 2018-01-18
15:45		 Hiroshima   Study on Deployment of a Computer Algebra System for Generating Random Test Patterns for Combinational Circuits
Tsutomu Inamoto, Yoshinobu Higami (Ehime Univ.) MSS2017-57 SS2017-44		 In this study, the authors display an attempt of deploying a computer algebra system to improve the fault detection rate... [more] MSS2017-57 SS2017-44
pp.59-64
VLD, CAS, MSS, SIP 2016-06-16
10:10		 Aomori Hirosaki Shiritsu Kanko-kan Automatic Test Pattern Generation for Multiple Stuck-At Faults: When Testing for Single Faults is Insufficient
Conrad JinYong Moore, Amir Masoud Gharehbaghi, Masahiro Fujita (Univ. of Tokyo) CAS2016-3 VLD2016-9 SIP2016-37 MSS2016-3		 As fabricated circuitry gets larger and denser, modern industrial ATPG techniques which focus on the detection of single... [more] CAS2016-3 VLD2016-9 SIP2016-37 MSS2016-3
pp.13-18
SDM 2010-11-12
13:50		 Tokyo Kikai-Shinko-Kaikan Bldg. Modeling of Single-Event-Transient Pulse Generation in Inverter Cells
Katsuhiko Tanaka, Hideyuki Nakamura, Taiki Uemura, Kan Takeuchi, Toshikazu Fukuda, Shigetaka Kumashiro, Tohru Mogami (MIRAI-Selete) SDM2010-180		 Soft errors in logic circuits due to the propagation of erroneous signal caused by ionized particle generated by cosmic ... [more] SDM2010-180
pp.47-52
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