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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IN | 2019-01-21 16:00 |
Aichi | WINC AICHI | Improvement of FQ-Codel by gradually increasing packet drop interval Kyosuke Kubota, Shigetomo Kimura (Univ. of Tsukuba)  IN2018-78 |
Nowadays, the buffer size of routers and switches has increased. When Internet traffic increases, the number of packets... [more] | IN2018-78 pp.37-42 |
| SANE | 2018-06-22 15:40 |
Ibaraki | Tsukuba Space Center, JAXA | VCM System with Only Variable Modulation Scheduling According to Satellite Elevation Angle Chihaya Kato, Mitsuhiro Nakadai, Yajima Masanobu (JAXA) SANE2018-19 |
Recently, researches and developments of higher-order modulation and broadband telecommunication systems become more int... [more] | SANE2018-19 pp.33-37 |
| WBS, IT, ISEC | 2018-03-09 10:50 |
Tokyo | Katsusika Campas, Tokyo University of Science | Efficient Scheduling of Serial Iterative Decoding for Zigzag Decodable Fountain Codes Yoshihiro Murayama, Takayuki Nozaki (Yamaguchi Univ.) IT2017-129 ISEC2017-117 WBS2017-110 |
Fountain codes are erasure correcting codes realizing reliable communication systems for the multicast in the Internet. ... [more] |
IT2017-129 ISEC2017-117 WBS2017-110 pp.155-160 |
| SIP, IT, RCS | 2018-01-23 16:25 |
Kagawa | Sunport Hall Takamatsu | Evaluation of Coded Caching Scheme in Multi-rate Wireless Network Makoto Takita (Kobe Univ.), Masanori Hirotomo (Saga Univ.), Masakatu Morii (Kobe Univ.) IT2017-102 SIP2017-110 RCS2017-316 |
The network load is increasing due to the spread of content distribution services. Caching is known as a technique to r... [more] |
IT2017-102 SIP2017-110 RCS2017-316 pp.273-278 |
| RCS | 2017-10-19 15:55 |
Miyagi | Tohoku Institute of Technology | [Invited Lecture]
Massive Connect IoT Using QZSS/GPS High Accuracy Time and Position Information Suguru Kameda (Tohoku Univ.), Hiroshi Oguma (NIT, Toyama College), Noriharu Suematsu (Tohoku Univ.) RCS2017-183 |
The next generation information network is expected to further develop as a social infrastructure in all fields such as ... [more] | RCS2017-183 p.87 |
| RCS | 2016-04-21 20:00 |
Aomori | Romantopia, A Landscape of Forest and Stars, Hirosaki City | [Invited Lecture]
A study on sparse chaos code multiple access scheme for physical layer security Eiji Okamoto, Keisuke Kunitomo (NITech) RCS2016-8 |
To realize higher-capacity wireless access systems, a non-orthogonal multiple access (NOMA) scheme, in which a superimpo... [more] | RCS2016-8 pp.41-46 |
| RCS, CCS, SR, SRW (Joint) |
2016-03-03 10:50 |
Tokyo | Tokyo Institute of Technology | Performance comparison of SCMA, LDS, and OFDMA transmissions in uplink channels Eiji Okamoto, Keisuke Kunitomo (NITech), Hidenori Akita, Takuma Kyo (DENSO) RCS2015-366 |
In mobile uplink channels of advanced driver assistance systems, transmission schemes with low-latency, high-quality, an... [more] | RCS2015-366 pp.199-204 |
| RCS | 2014-06-18 10:21 |
Okinawa | Okinawa-ken Seinenkaikan (Naha) | Throughput Performance of Turbo Coded Single-Carrier Transmission with Frequency-Domain Puncturing Shohei Nakajima (Tokyo Univ. of Science), Kazuki Takeda (NTT DOCOMO), Kenichi Higuchi (Tokyo Univ. of Science) RCS2014-66 |
This paper investigates the throughput performance of turbo coded single-carrier transmission with our previously report... [more] | RCS2014-66 pp.197-202 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 16:45 |
Kanagawa | Hiyoshi Campus, Keio University | Binary Synthesis of Hardware Accelerator Tightly Coupled with CPU Shimpei Tamura, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Kanbara (ASTEM), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2013-133 CPSY2013-104 RECONF2013-87 |
This article presents a method of synthesizing hardware that accelerates specified sections of binary programs. The acce... [more] | VLD2013-133 CPSY2013-104 RECONF2013-87 pp.185-190 |
| RCS, AP (Joint) |
2013-11-20 14:00 |
Shimane | Matsue Terrsa | Comparison of Beamforming Matrix Control Methods in Base Station Cooperative Multiuser MIMO Using Block-Diagonalized Beamforming Matrix Nobuhide Nonaka (Tokyo Univ. of Science), Yuichi Kakishima (NTT DOCOMO), Kenichi Higuchi (Tokyo Univ. of Science) RCS2013-176 |
This paper investigates beamforming control method in the base station (BS) cooperative multiuser multiple-input multipl... [more] | RCS2013-176 pp.13-18 |
| DC, CPSY (Joint) |
2013-08-02 17:30 |
Fukuoka | Kitakyushu-Kokusai-Kaigijyo | Code Optimization for Path Based Speculative Multi-threading Yuki Homma, Hiroyoshi Jutori, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota (Utsunomiya Univ.) CPSY2013-28 |
Our Two-Path Limited Speculation system PALS speculatively executes one of the top two paths of high frequency in loops.... [more] | CPSY2013-28 pp.109-114 |
| IN, RCS (Joint) |
2012-05-18 09:20 |
Tokyo | Kuramae-Kaikan, Tokyo Institute of Technology | User scheduling in MU-MIMO system considering codebook design and interference among users Ikuma Ando, Gia Khanh Tran, Kei Sakaguchi, Kiyomichi Araki (Tokyo Tech Univ.) RCS2012-32 |
Recently, multiuser MIMO communication system has attracted much attention because of their potential for increasing ra... [more] |
RCS2012-32 pp.61-66 |
| SAT | 2011-12-12 09:25 |
Aichi | Nagoya University | A Computationally Efficient Early Stopping Method for DVB-S2 LDPC Decoder Gwan Seok Jang (UST-ETRI), In Ki Lee, Dae Ig Chang, Deock Gil Oh (ETRI) SAT2011-40 |
Satellite communication requires powerful forward error correction scheme because of long transmission delay. Thus, the ... [more] | SAT2011-40 pp.7-12 |
| SIP, CAS, CS | 2010-03-02 09:20 |
Okinawa | Hotel Breeze Bay Marina, Miyakojima | Preprocessing Method based on Operation Instruction Clustering of Code Optimization for a Processor Architecture with Bypass Chain Yuki Kamada, Toshihiro Shoji, Jin Tian, Nobuhiko Sugino (Tokyou Inst. of Tech.) CAS2009-108 SIP2009-153 CS2009-103 |
For a processor with a bypass chain, a novel code optimization method based on data flow graph (DFG) form is discussed. ... [more] | CAS2009-108 SIP2009-153 CS2009-103 pp.173-178 |
| VLD | 2009-03-11 10:30 |
Okinawa | Optimum Code Scheduling for VLIW DSP SPXK5 considering Conditional Execution Tetsuya Yamamoto, Nagisa Ishiura (Kwansei Gakuin Univ.), Takahiro Kumura, Masao Ikekawa (NEC), Masaharu Imai (Osaka Univ.) VLD2008-126 |
This article presents an optimum code scheduling method for digital signal processor SPXK5 taking account of its archite... [more] | VLD2008-126 pp.1-6 |
|
| IT | 2008-09-11 17:55 |
Okinawa | Culture Resort Festone (Okinawa) | Complexity-reducing Algorithm for Serial Min-sum Decoding Hironori Uchikawa, Kohsuke Harada, Yasuhiko Tanabe (Toshiba) IT2008-28 |
We propose a complexity-reducing algorithm for serial min-sum decoding that reduces the number of check nodes to proce... [more] |
IT2008-28 pp.49-54 |
| CPSY | 2007-12-19 14:35 |
Kyoto | Campus Plaza Kyoto | A Scheduling of Shuffled BP Decoding Considering Pipelining Delay Kazuya Yokohari, Yoshihiro Sugaya, Hirotomo Aso (Tohoku Univ.) CPSY2007-44 |
Shuffled BP decoding is known as a decoding method which has good decoding performance for low-density parity-check (LDP... [more] | CPSY2007-44 pp.21-26 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-22 14:55 |
Fukuoka | Kitakyushu International Conference Center | Cycle Partitioned Scheduling for Code Optimization of VLIW DSP Yuuki Masui, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2007-102 DC2007-57 |
This paper proposes a cycle partitioned scheduling method for code optimization of VLIW DSPs. The previously proposed op... [more] | VLD2007-102 DC2007-57 pp.79-84 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-22 15:20 |
Fukuoka | Kitakyushu International Conference Center | Retargetable Linear Assembler for VLIW Processor Satoshi Nogaito, Nagisa Ishiura (Kwansei Gakuin Univ.), Masaharu Imai (Osaka Univ.) VLD2007-103 DC2007-58 |
This paper proposes a retargetable linear assembler as a software development tool for custom VLIW processors. The ret... [more] |
VLD2007-103 DC2007-58 pp.85-90 |
| VLD, ICD, DC, IPSJ-SLDM | 2005-12-02 11:00 |
Fukuoka | Kitakyushu International Conference Center | Handling of Variables and Functions for Software Compatible Hardware Synthesizer CCAP Kenichi Nishiguchi, Nagisa Ishiura, Masanari Nishimura (Kwansei Gakuin Univ.), Hiroyuki Kanbara (ASTEM), Hiroyuki Tomiyama (Nagoya Univ.), Yutetsu Takatsukasa, Manabu Kotani (Kyoto Univ.) |
We are developing a high-level synthesis tool named CCAP (C Compatible Architecture Prototyper), which synthesizes arbit... [more] | VLD2005-79 ICD2005-174 DC2005-56 pp.19-24 |
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