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Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF 2011-09-26
13:30		 Aichi Nagoya Univ. A Novel Cluster Structure based on Input Sharing of LUTs
Toshiya Takahashi, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2011-25		 Cluster-based FPGAs are composed of logic clusters having LUTs which are basic logic elements.
At each of logic cluster... [more]		 RECONF2011-25
pp.19-24
RECONF, VLD, CPSY, IPSJ-SLDM [detail] 2011-01-18
11:15		 Kanagawa Keio Univ (Hiyoshi Campus) Optimization of Local Routing Networks in a Logic Block for Cluster Based FPGAs
Yuji Masumitsu, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) VLD2010-104 CPSY2010-59 RECONF2010-73		 Feild programmable gate arrays (FPGAs) are mostly cluseter-based FPGAs. In a cluster-based FPGA, a logic block consists ... [more] VLD2010-104 CPSY2010-59 RECONF2010-73
pp.139-144
RECONF 2009-09-17
14:50		 Tochigi Utsunomiya Univ. Low-power oriented clustering and placement tools using routability for FPGAs
Shinya Imaizumi, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2009-23		 Power consumption of Field Programmable Gate Arrays (FPGAs) is larger than Application Specific Integrated Circuits (ASI... [more] RECONF2009-23
pp.25-30
RECONF 2009-05-15
10:00		 Fukui   A low-power clustering tool using both routability and activity for FPGAs
Junya Eto, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2009-10		 Although FPGA(Field Programmable Gate Array) has high exibility, there is a problem that power consumption is larger tha... [more] RECONF2009-10
pp.55-60
RECONF 2005-05-12
10:00		 Kyoto Kyoto University Development of clustering tool to reduce area of chip and delay
Masaki Kobata, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) 		In this paper,we present a clustering technique for area and delay reduction in clustered FPGAs.
This technique uses tw... [more]		 RECONF2005-2
pp.7-12
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