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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD, CAS, MSS, SIP |
2016-06-17 15:10 |
Aomori |
Hirosaki Shiritsu Kanko-kan |
Clock Distribution Network with Multiple Source Buffers for Stacked Chips Nanako Niioka, Masashi Imai, Kaoru Furumi, Atsushi Kurokawa (Hirosaki Univ.) CAS2016-31 VLD2016-37 SIP2016-65 MSS2016-31 |
In this report, we present a method to reduce clock skew among stacked chips by a clock distribution network with multip... [more] |
CAS2016-31 VLD2016-37 SIP2016-65 MSS2016-31 pp.167-172 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 15:35 |
Oita |
B-ConPlaza |
Energy-efficient High-level Synthesis Algorithm targeting HDR-mcv Architecture with Multiple Clock Domains and Multiple Supply Voltages Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Institute of Technology/Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-102 DC2014-56 |
An HDR-mcv architecture, which integrates multiple supply voltages and multiple clock domains into high-level synthesis ... [more] |
VLD2014-102 DC2014-56 pp.203-208 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 13:50 |
Fukuoka |
Centennial Hall Kyushu University School of Medicine |
Energy-efficient High-level Synthesis Considering Clock Design for HDR Architectures Hiroyuki Akasaka, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2012-81 DC2012-47 |
With the miniaturization of LSIs and its increasing performance, demand for high-functional portable devices has grown s... [more] |
VLD2012-81 DC2012-47 pp.129-134 |
VLD |
2009-03-11 15:50 |
Okinawa |
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A Lower Cost Clock Tree Synthesis Method in General-Synchronous Framework using an EDA tool Hiroyoshi Hashimoto, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech.) VLD2008-134 |
Clock trees for general synchronous framework can be synthesized by using a clock tree synthesis (CTS) engine in EDA sys... [more] |
VLD2008-134 pp.47-52 |
CAS |
2008-02-01 10:55 |
Okinawa |
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A Fast Modification Algorithm for Shortest Path Tree and its Performance Evaluation Tsutomu Ishida, Yukihide Kohira, Atsushi Takahashi (Tokyo Tech) CAS2007-98 |
In VLSI design, circuits are improved by circuit modifications.The minimum feasible clock period of a circuit is one of ... [more] |
CAS2007-98 pp.25-30 |
ICD, SIP, IE, IPSJ-SLDM |
2006-10-27 13:10 |
Miyagi |
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[Invited Talk]
General synchronous circuits using global clock
-- design methodologies, tools, and prospects -- Atsushi Takahashi (Tokyo Inst. of Tech.) |
In current VLSI design, most digital circuits are synthesized as synchronous circuits which are synchronized by global c... [more] |
SIP2006-110 ICD2006-136 IE2006-88 pp.55-60 |
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