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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| NS | 2023-10-05 09:45 |
Hokkaido | Hokkaidou University + Online (Primary: On-site, Secondary: Online) |
[Encouragement Talk]
Performance Evaluation of D2D Caching Method Using LSTM Considering Missing Data Makoto Tsunekiyo (Fukuoka Univ.), Noriaki Kamiyama (Ritsumeikan Univ.)  NS2023-85 |
As video viewing on mobile terminals becomes more common, there is concern that the backhaul traffic load on cellular ne... [more] | NS2023-85 pp.77-82 |
| HWS, VLD | 2023-03-02 16:50 |
Okinawa | (Primary: On-site, Secondary: Online) |
Reducing Conflict Misses with Multiple Indexings in Compressed Caches Tasuku Fukami, Shinya Takamaeda (UTokyo) VLD2022-98 HWS2022-69 |
Cache memory is a common hardware mechanism that improves memory access performance. To enlarge cache capacity virtually... [more] | VLD2022-98 HWS2022-69 pp.131-136 |
| RCS, SIP, IT | 2022-01-20 10:55 |
Online | Online | Design of Coded Caching for Multi-User MISO Channels with Heterogeneous Cache Sizes Ayaka Urabe, Koji Ishibashi (UEC), MohammadJavad Salehi, Antti Tolli (Univ. Oulu) IT2021-38 SIP2021-46 RCS2021-206 |
This paper focuses on coded caching when every user has a different memory size for caching and studies the design over ... [more] | IT2021-38 SIP2021-46 RCS2021-206 pp.57-62 |
| RCS, SR, SRW (Joint) |
2021-03-05 10:55 |
Online | Online | Beamforming Design for Heterogeneous Wireless Systems with Coded-Caching Ayaka Urabe, Koji Ishibashi (UEC) RCS2020-256 |
In this paper, we propose a transmission beamforming design for the multiple input single output (MISO) system consistin... [more] | RCS2020-256 pp.246-251 |
| CPSY, DC, IPSJ-ARC [detail] | 2020-07-30 11:00 |
Online | Online | Instruction Prefetcher focusing on properties of Prefetch Distance Tomoki Nakamura, Toru Koizumi, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya (UTokyo) CPSY2020-1 DC2020-1 |
Instruction cache misses and branch target buffer (BTB) misses are performance bottlenecks in recent applications, and ... [more] |
CPSY2020-1 DC2020-1 pp.1-8 |
| NS, IN (Joint) |
2020-03-06 15:30 |
Okinawa | Royal Hotel Okinawa Zanpa-Misaki (Cancelled but technical report was issued) |
Learning Content Transmission Method in Delayed Update-Tolerant Web Cache Servers for E-learning Support in Developing Country Yudai Kurashita, Kazumasa Takami (Soka Univ.) IN2019-147 |
In 2017, there were 123 million children who were unable to go to school, that is a serious problem. To support educatio... [more] | IN2019-147 pp.411-416 |
| NS, IN, CS, NV (Joint) |
2019-09-06 11:15 |
Miyagi | Research Institute of Electrical Communication, Tohoku Univ. | A Study on Features Derived from Cache Property for DNS Tunneling Detection Naotake Ishikura, Daishi Kondo, Hideki Tode (Osaka Pref. Univ.) NS2019-93 |
A lot of enterprises are under threat of targeted attacks causing data exfiltration, and as a means of performing the at... [more] | NS2019-93 pp.25-30 |
| NS, IN (Joint) |
2017-03-02 10:10 |
Okinawa | OKINAWA ZANPAMISAKI ROYAL HOTEL | Improvement of Cache Reference Rate in Information-Centric Networking-based Wireless Sensor Network Masafumi Koike, Osamu Mizuno (Kogakuin Univ.) IN2016-117 |
We proposed to wireless sensor network applying ICN(Information-Centric Networking) to provide a variety of M2M services... [more] | IN2016-117 pp.121-126 |
| VLD | 2017-03-01 14:00 |
Okinawa | Okinawa Seinen Kaikan | Fine-Grain Power Gating of MTJ-based Non-volatile Cache and Dynamic Selection Control for Storing Cache Lines Shota Enokido, Kimiyoshi Usami (SIT) VLD2016-102 |
Non-volatile Power Gating(NVPG) is a technique to power gate memory elements to reduce leakage power while keeping the s... [more] | VLD2016-102 pp.1-6 |
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2016-08-09 10:30 |
Nagano | Kissei-Bunka-Hall (Matsumoto) | High Performance of Cache by Dynamic Control to Area Division Maika Tone, Takahiro Sasaki, Yuki Fukazawa, Toshio Kondo (Mie Univ.) CPSY2016-19 |
Today, multi-core processor is widely used to improve performance of a processor. However, memory access frequency of m... [more] |
CPSY2016-19 pp.119-124 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 14:10 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Exploration of Address Offsets of Basic Blocks for Cache Hit Ratio Improvement Junya Goto, Nagisa Ishiura (K.G.) VLD2015-74 DC2015-70 |
This article proposes a method of reducing cache misses on an instruction memory by inserting offsets before basic block... [more] | VLD2015-74 DC2015-70 pp.237-241 |
| ICD, IE, VLD, IPSJ-SLDM [detail] | 2015-10-26 15:25 |
Miyagi | A Power-Efficient Memory Hierarchy Design for the 3D Integration Era Wataru Uno, Masayuki Sato, Ryusuke Egawa, Hiroaki Kobayashi (Tohoku Univ.) VLD2015-30 ICD2015-43 IE2015-65 |
3D-stacked memories are expected to play key roles to realize high-performance and low-power computing systems. This pap... [more] | VLD2015-30 ICD2015-43 IE2015-65 pp.19-24 |
|
| IA, ICSS | 2015-06-11 15:45 |
Fukuoka | Kyushu Institute of Technology Univ. | The Analysis of the CREAM vulnerability against OpenSSL Jun Hasegawa, Yuhei Watanabe, Masakatu Morii (Kobe Univ.) IA2015-6 ICSS2015-6 |
In this paper we discuss vulnerability of "CREAM", which was originally created by Daniel J. Bernstein in 2005 and named... [more] | IA2015-6 ICSS2015-6 pp.27-32 |
| CS | 2014-11-07 09:00 |
Hokkaido | Shiretoko (Hokkaido) | Time to Hold (TTH), an Optimal Cache Replacement Policy for Video Delivery on CCN Haipeng Li, Hidenori Nakazato (Waseda Univ.) CS2014-65 |
In-network caching, one of the characteristics of Content Centric Networking (CCN), allows the contents to be cached alo... [more] | CS2014-65 pp.69-74 |
| CPSY, DC | 2014-04-25 15:15 |
Tokyo | A Hardware Cache Mechanism for Column-Oriented Databases Akihiko Hamada, Hiroki Matsutani (Keio Univ.) CPSY2014-5 DC2014-5 |
A column-oriented store is one of structured storages (NOSQLs), in which a variable number of columns can be stored for... [more] |
CPSY2014-5 DC2014-5 pp.21-26 |
|
| CQ, MoNA, IPSJ-DPS, IPSJ-CN, IPSJ-EIP (Joint) [detail] |
2013-09-12 14:25 |
Ishikawa | Kanazawa Institute of Technology | Traffic-based Flow Cache Port Separate Mechanism for Network Processor Hayato Yamaki, Hiroaki Nishi (Keio Univ.) CQ2013-36 |
A mechanism called Flow cache, which classifies packets into flows and caches the results of header rewrite that is equa... [more] | CQ2013-36 pp.47-52 |
| NS, IN (Joint) |
2013-03-07 11:10 |
Okinawa | Okinawa Zanpamisaki Royal Hotel | High quality streaming using disjoint paths under hierarchical cache-servers environment Akihiro Fujimoto, Yusuke Hirota (Osaka Univ.), Hideki Tode (Osaka Pref. Univ.), Koso Murakami (Osaka Univ.) NS2012-206 |
Video streaming using hierarchical cache servers is effective to provide high quality services to many users. However, w... [more] | NS2012-206 pp.237-242 |
| NS, IN (Joint) |
2012-03-08 10:30 |
Miyazaki | Miyazaki Seagia | Energy Awareness based on Cache Allocation Management in Content-Centric Networking Satoshi Imai (Fujitsu lab.), Kenji Leibnitz (NICT), Masayuki Murata (Handai) IN2011-140 |
Power consumption of network devices has been increasing together with traffic volume and it is therefore important to f... [more] | IN2011-140 pp.19-24 |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-25 15:05 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | Simultaneous Optimization of Cache Way Selection and Code Placement for Reducing the Memory Access Energy Consumption Junshi Takata (Kyushu Univ.), Tohru Ishihara (Kyoto Univ.), Koji Inoue (Kyushu Univ.) SIP2011-76 ICD2011-79 IE2011-75 |
The paper proposes a technique which simultaneously finds the optimal cache way allocation and code placement for given ... [more] | SIP2011-76 ICD2011-79 IE2011-75 pp.89-94 |
| VLD | 2011-03-02 14:00 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | Exact, Fast and Flexible Two-level Cache Simulation for Embedded Systems Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ.) VLD2010-118 |
In hierarchical cache configurations, L1 cache uses LRU as cache replacement policy but L2 and/or L3 caches use FIFO du... [more] |
VLD2010-118 pp.13-18 |
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