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Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2012-02-13
14:25		 Tokyo Kikai-Shinko-Kaikan Bldg. A method to reduce the number of test patterns for transition faults using control point insertions
Akihiko Takahashi, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ) DC2011-82		 In recent year, the growing density and complexity for VLSIs cause an increase in the number of test patterns. Moreover,... [more] DC2011-82
pp.37-42
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2010-11-29
15:45		 Fukuoka Kyushu University A decision method of target detected pseudo primary outputs on Low-capture-swithing-activity test generation
Yang Shen, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ) VLD2010-62 DC2010-29		 High launch switching activity in capture mode during at-speed scan testing may lead to excessive IR-drop. Excessive IR-... [more] VLD2010-62 DC2010-29
pp.37-42
DC 2010-02-15
13:45		 Tokyo Kikai-Shinko-Kaikan Bldg. A Test Compaction Oriented Control Point Insertion Method for Transition Faults
Yoshitaka Yumoto, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyusyu Univ.) DC2009-72		 The recent advances in semiconductor processing technology have resulted in the exponential increase in LSI circuit dens... [more] DC2009-72
pp.45-50
VLD, ICD, DC, IPSJ-SLDM 2005-12-02
09:55		 Fukuoka Kitakyushu International Conference Center A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
Tsuyoshi Iwagaki (JAIST), Satoshi Ohtake, Hideo Fujiwara (NAIST) 		This paper presents a broadside test generation method for
transition faults in partial scan circuits. In order to gene... [more]		 VLD2005-77 ICD2005-172 DC2005-54
pp.7-12
 Results 1 - 4 of 4  /   
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