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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 4 of 4  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
CAS, SIP, MSS, VLD, SIS [detail] 2014-07-09
13:40
Hokkaido Hokkaido University Weighted Dominating Sets and Induced Matchings in Orthogonal Ray Graphs
Asahi Takaoka, Satoshi Tayu, Shuichi Ueno (Tokyo Inst. of Tech.) CAS2014-10 VLD2014-19 SIP2014-31 MSS2014-10 SIS2014-10
An orthogonal ray graph is an intersection graph of horizontal rays (closed half-lines) and vertical rays in the plane. ... [more] CAS2014-10 VLD2014-19 SIP2014-31 MSS2014-10 SIS2014-10
pp.45-48
CAS, SIP, MSS, VLD, SIS [detail] 2014-07-11
13:00
Hokkaido Hokkaido University Accelerating Boolean Matching of LUT-based Circuits using CEGAR method
Yusuke Matsunaga (Kyushu Univ.) CAS2014-38 VLD2014-47 SIP2014-59 MSS2014-38 SIS2014-38
This paper describes an accelerating technique for Boolean matching of LUT-based circuits, which is based on CEGAR (coun... [more] CAS2014-38 VLD2014-47 SIP2014-59 MSS2014-38 SIS2014-38
pp.201-206
IPSJ-SLDM, CPSY, RECONF, VLD [detail] 2014-01-29
13:45
Kanagawa Hiyoshi Campus, Keio University On Boolean Matching of LUT-based Circuits
Yusuke Matsunaga (Kyushu Univ.) VLD2013-127 CPSY2013-98 RECONF2013-81
This paper describes two speed-up techniques for Boolean matching of
LUT-based circuits.
One is one-hot encoding tec... [more]
VLD2013-127 CPSY2013-98 RECONF2013-81
pp.149-154
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]
2007-11-20
15:35
Fukuoka Kitakyushu International Conference Center A Study of Conection Block Structure and Implementation Methods of Multi-Input Functions for Variable Grain Logic Cell
Kazunori Matsuyama, Ryoichi Yamaguchi, Yoshiaki Satou, Hiroshi Miura, Masahiro Koga, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2007-33
Since VGLC(Variable Grain Logic Cell) has a feature set both coarse-grained and fine-grained
types, its structure can ... [more]
RECONF2007-33
pp.7-12
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