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 Results 1 - 8 of 8  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, DC, IPSJ-ARC
(Joint) [detail]
2015-08-05
14:30
Oita B-Con Plaza (Beppu) Efficient Thread Control Method for Parallel Loop Processing by Dynamic Binary Translation
Hiroyuki Obuchi, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota (Utsunomiya Univ.) CPSY2015-29
In order to effectively utilize the performance of multicore processors spreading commonly at present, it is an importan... [more] CPSY2015-29
pp.155-160
DC, CPSY
(Joint)
2013-08-02
14:30
Fukuoka Kitakyushu-Kokusai-Kaigijyo Reduction of Runtime Overhead in Automated Parallel Processing System using Valgrind
Takayuki Hoshi, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota (Utsunomiya Univ.) CPSY2013-23
In order to efficiently utilize the performance of multicore processors, thread level parallel processing is indispensab... [more] CPSY2013-23
pp.79-84
CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] 2012-03-03
11:00
Miyagi   An Automatic Parallelization Scheme Used in JIT Compilation for Dynamic Language Applications
Ryotaro Ikeda, Nobuhiko Sugino (Tokyo Tech) CPSY2011-90 DC2011-94
An automatic parallelization scheme for dynamic language applications under interpreter ex-ecution environment is propos... [more] CPSY2011-90 DC2011-94
pp.187-192
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2010-12-01
09:50
Fukuoka Kyushu University Preliminary Evaluation of Automatic Thread-Level Parallelization using Binary-Level Variable Analysis
Takashi Shiroto, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2010-37
Recently, the multi-core processors are widely available.
For effective utilization of the performance of multi-core pr... [more]
CPSY2010-37
pp.31-36
SIP, CAS, CS 2010-03-02
13:45
Okinawa Hotel Breeze Bay Marina, Miyakojima [Poster Presentation] Automatic Code Parallelization base on quantitative evaluation of data transfer for multi-layered cache architecture
Takuya Noritake, Nobuhiko Sugino (Tokyo Inst. of Tech.) CAS2009-119 SIP2009-164 CS2009-114
An automatic code parallelization method based on quantitative evaluation of data transfer for multi-layered cache archi... [more] CAS2009-119 SIP2009-164 CS2009-114
pp.235-236
ICD, IPSJ-ARC 2008-05-14
13:45
Tokyo   Automatic Parallelization of Restricted C Programs using Pointer Analysis
Masayoshi Mase (Waseda Univ.), Daisuke Baba (Waseda Univ. / Matsushita Electric Industrial), Harumi Nagayama (Waseda Univ. / Intel), Yuta Murata, Keiji Kimura, Hironori Kasahara (Waseda Univ.)
This paper describes a restriction on pointer usage in C language for parallelism extraction by an automatic parallelizi... [more] ICD2008-30
pp.69-74
RECONF, CPSY, VLD, IPSJ-SLDM 2008-01-17
16:50
Kanagawa Hiyoshi Campus, Keio University VLIW Extension of Software Development Environment Construction Tool ArchC
Takanori Morimoto (Kwansei Gakuin Univ.), Takahiro Kumura (NEC), Nagisa Ishiura (Kwansei Gakuin Univ.), Masao Ikekawa (NEC), Masaharu Imai (Osaka Univ.) VLD2007-134 CPSY2007-77 RECONF2007-80
ArchC is a C++/SystemC-based open-source software,which generates software development environments (consisting of Binut... [more] VLD2007-134 CPSY2007-77 RECONF2007-80
pp.95-100
ICD, IPSJ-ARC 2007-05-31
13:45
Kanagawa   Mutligrain Parallel Processing in SMP Execution Mode on a Multicore for Consumer Electronics
Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Hiroaki Tano, Takeshi Masuura, Takamichi Miyamoto, Jun Shirako, Hirofumi Nakano, Keiji Kimura (Waseda Univ.), Tatsuya Kamei, Toshihiro Hattori, Atsushi Hasegawa (Renesas Technology), Masaki Ito, Makoto Satoh, Kunio Uchiyama (Hitachi Ltd.)
Currently, multicore processors are becoming ubiquitous in various computing domains, namely con-
sumer electronics suc... [more]
ICD2007-21
pp.25-30
 Results 1 - 8 of 8  /   
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