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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 53  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM, ICD, ITE-IST [detail] 2021-08-18
15:35
Online Online Evaluation of Side-channel Leakage on High-speed Asynchronous Successive Approximation Register AD Converters
Ryozo Takahashi, Kazuki Monta, Takuji Miki, Makoto Nagata (Kobe Univ.) SDM2021-43 ICD2021-14
This paper presents an evaluation of security level on high-speed asynchronous successive approximation register (SAR) a... [more] SDM2021-43 ICD2021-14
pp.68-71
HWS, VLD [detail] 2020-03-04
13:25
Okinawa Okinawa Ken Seinen Kaikan
(Cancelled but technical report was issued)
A Study of Dynamic Power Optimization by Latch Insertion for Asynchronous RTL Models
Shogo Semba, Hiroshi Saito (UoA) VLD2019-100 HWS2019-73
In this paper, we propose a dynamic power optimization method by latch insertion for asynchronous RTL models. In data-pa... [more] VLD2019-100 HWS2019-73
pp.37-42
HWS, ICD [detail] 2019-11-01
16:00
Osaka DNP Namba SS Bld. A Study of Hardware Trojan Detection Method using Deep Learning in Asynchronous Circuits
Hikaru Inafune, Masashi Imai (Hirosaki Univ.) HWS2019-63 ICD2019-24
There are typically two timing methods in VLSI designs known as
synchronous circuits which use a global clock and async... [more]
HWS2019-63 ICD2019-24
pp.35-40
MSS, CAS, SIP, VLD 2019-07-31
16:45
Iwate Iwate Univ. Speedup of the Asynchronous Serial Multiplier by Concealing the Idle Phase for Digital Hearing Aids
Masahiro Nagata (Okayama Prefectural Univ.), Masafumi Kondo, Isao Kayono (Kawasaki Univ. of Medical Welfare), Tomoyuki Yokogawa, Kazutami Arimoto, Yoichiro Sato (Okayama Prefectural Univ.) CAS2019-22 VLD2019-28 SIP2019-38 MSS2019-22
Recently, digital hearing aids with DSP have spread through, but their battery life has remained for only a few days. Fo... [more] CAS2019-22 VLD2019-28 SIP2019-38 MSS2019-22
pp.99-104
HWS, VLD 2019-03-01
10:25
Okinawa Okinawa Ken Seinen Kaikan A Study on Placement Constraints for Asynchronous Circuits with Bundled-data Implementation aimed for FPGAs
Tatsuki Otake, Hiroshi Saito (UoA) VLD2018-123 HWS2018-86
In this work, we study placement constraints for asynchronous circuits with bundled-data implemen-tation aimed for Field... [more] VLD2018-123 HWS2018-86
pp.181-186
VLD, HWS
(Joint)
2018-03-01
13:25
Okinawa Okinawa Seinen Kaikan A Study on Energy Optimization for Asynchronous RTL Models with Bundled-data Implementation
Shogo Semba, Hiroshi Saito (UoA) VLD2017-111
In this work, we study two energy optimization methods for asynchronous RTL models with bundled-data implementation. The... [more] VLD2017-111
pp.133-138
VLD 2017-03-01
16:20
Okinawa Okinawa Seinen Kaikan Implementation of a Transformation tool from Synchronous RTL Models to Asynchronous RTL Models
Shogo Senba, Hiroshi Saito (UoA) VLD2016-107
This paper proposes a transformation tool that generates an asynchronous Register Transfer Level (RTL) model with bundle... [more] VLD2016-107
pp.31-36
VLD, CAS, MSS, SIP 2016-06-17
15:50
Aomori Hirosaki Shiritsu Kanko-kan A Study on Fault Tolerant Features of Asynchronous Circuits using Voted-enable Latches
Masashi Imai (Hirosaki Univ.), Tomohiro Yoneda (NII) CAS2016-33 VLD2016-39 SIP2016-67 MSS2016-33
A bit flip caused by voltage fluctuation, soft errors, and hardware Trojans becomes one of serious issues in the modern ... [more] CAS2016-33 VLD2016-39 SIP2016-67 MSS2016-33
pp.179-184
NLP 2016-03-24
13:25
Kyoto Kyoto Sangyo Univ. Implementation of Boltzmann Machine by Asynchronous Network of Cellular Automaton-based Neurons
Takashi Matsubara, Kuniaki Uehara (Kove Univ.) NLP2015-143
Artificial neural networks with stochastic state transitions, such as Deep Boltzmann Machine, have excelled other machin... [more] NLP2015-143
pp.7-10
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-03
09:20
Nagasaki Nagasaki Kinro Fukushi Kaikan A Handshake-delay-aware Scheduling Algorithm in High-level Synthesis for Four-phase Dual-rail Asynchronous Systems
Kohta Itani, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2015-60 DC2015-56
This report is intended to discuss the scheduling problem in high-level synthesis~(HLS) for four-phase dual-rail asynchr... [more] VLD2015-60 DC2015-56
pp.147-152
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-03
13:45
Nagasaki Nagasaki Kinro Fukushi Kaikan Evaluation of Low-Voltage Characteristics of QDI model based Asynchronous VLSI
Ryuhei Tachika, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.) VLD2015-67 DC2015-63
In synchronous circuits, it is needed to distribute an identical clock signal to the whole chip with a constant frequenc... [more] VLD2015-67 DC2015-63
pp.189-194
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-03
14:10
Nagasaki Nagasaki Kinro Fukushi Kaikan Implementation and Evaluation of Peak Current Reduction Bandpass Filter using Asynchronous Circuits
Tatsuya Ishikawa, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.) VLD2015-68 DC2015-64
In synchronous circuits, peak currents flow at a constant frequency since a global clock signal which is a timing signal... [more] VLD2015-68 DC2015-64
pp.195-200
DC 2015-06-16
15:35
Tokyo Kikai-Shinko-Kaikan Bldg. A Study on Function Test of Latch-based Asynchronous Pipeline Circuits
Daiki Toyoshima, Kyohei Terayama, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.) DC2015-19
Asynchronous MOUSETRAP pipeline circuit is a simple and fast circuit thanks to the 2-phase handshaking protocol which ha... [more] DC2015-19
pp.19-24
SDM, EID 2014-12-12
14:00
Kyoto Kyoto University Characterization of Synchronous and Asynchronous Circuits using poly-Si TFTs
Yosuke Nagase (Ryukoku Univ.), Tokiyoshi Matsuda, Mutsumi Kimura (Osaka Univ.), Taketoshi Matsumoto, Hikaru Kobayashi (Ryukoku Univ.) EID2014-25 SDM2014-120
We have evaluated multiple-input NAND circuits using polycrystalline silicon thin-film transistors and found that the ou... [more] EID2014-25 SDM2014-120
pp.61-65
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
10:45
Oita B-ConPlaza A hardware description method and sematics providing a timing constrant
Shunji Nishimura, Motoki Amagasaki, Toshinori Sueyoshi (Kumamoto Univ.) VLD2014-82 DC2014-36
Formal verification methods are wide-spreading due to its mathmatical rigorousaspect, although they limited to synchroun... [more] VLD2014-82 DC2014-36
pp.81-86
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-28
14:45
Oita B-ConPlaza A Study of Power Optimization for Asynchronous Circuits with Bundled-data Implementation using Mobility of Operations
Shunya Hosaka, Hiroshi Saito (Univ. Aizu) VLD2014-104 DC2014-58
In this paper, we study a dynamic power optimization method for asynchronous circuits with bundled-data implementation u... [more] VLD2014-104 DC2014-58
pp.215-220
CAS, MSS, IPSJ-AL [detail] 2014-11-20
10:40
Okinawa Nobumoto Ohama Memorial Hall (Ishigaki island) An asynchronous serial multiplier for digital fearing aid
Masafumi Kondo, Daichi Okamoto (Kawasaki Univ. of Medical Welfare), Yoichiro Sato, Tomoyuki Yokogawa, Kazutami Arimoto (Okayama Prefectural Univ.) CAS2014-89 MSS2014-53
Recently, digital hearing aids with digital signal processor (DSP) become widely used because of increasing of hearing i... [more] CAS2014-89 MSS2014-53
pp.11-16
IE, ICD, VLD, IPSJ-SLDM [detail] 2014-10-02
14:15
Miyagi   Hierarchical GALS system based on ring segmented bus architecture
Masafumi Kondo (Kawasaki Univ. of Medical Welfare), Tomoyuki Yokogawa, Yoichiro Sato, Kazutami Arimoto (Okayama Prefectural Univ.) VLD2014-63 ICD2014-56 IE2014-42
A ring segmented bus (RSB) which connects the divided annular bus dynamically has been proposed as an asynchronous bus a... [more] VLD2014-63 ICD2014-56 IE2014-42
pp.19-24
CAS, SIP, MSS, VLD, SIS [detail] 2014-07-11
15:10
Hokkaido Hokkaido University A distributed asynchronous arbiter for ring segmented bus type GALS systems
Yoshiki Odagiri, Masaki Akari (Okayama Prefectural Univ.), Masafumi Kondo (Kawasaki Univ. of Medical Welfare), Tomoyuki Yokogawa, Yoichiro Sato, Kazutami Arimoto (Okayama Prefectural Univ.) CAS2014-44 VLD2014-53 SIP2014-65 MSS2014-44 SIS2014-44
A ring segmented bus (RSB) which connects the divided annular bus dynamically has been proposed for GALS systems. Howeve... [more] CAS2014-44 VLD2014-53 SIP2014-65 MSS2014-44 SIS2014-44
pp.237-242
RECONF 2014-06-12
10:50
Miyagi Katahira Sakura Hall An Asynchronous High-Performance FPGA Based on LEDR/Four-Phase-Dual-Rail Hybrid Architecture
Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) RECONF2014-6
This paper presents an asynchronous high-performance FPGA that combines Four-Phase Dual-Rail (FPDR) protocol and Level-E... [more] RECONF2014-6
pp.27-30
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