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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 13件中 1~13件目  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS 2019-04-12
15:05
Miyagi Tohoku University Implementation and Experimental Evaluation of Physically Unclonable Functions in 180nm CMOS Process
Mitsuru Shiozaki, Takaya Kubota, Masayoshi Shirahata (Ritsumeikan Univ.), Yohei Hori, Toshihiro Katashita (AIST), Takeshi Fujino (Ritsumeikan Univ.)
Evaluation items and evaluation schemes of Physically Unclonable Function (PUF) are discussed in international standardi... [more] HWS2019-4
pp.19-24
VLD, HWS
(Joint)
2018-03-02
14:30
Okinawa Okinawa Seinen Kaikan Modeling Attacks on Double-Arbiter PUF Using Deep Neural Network
Tomoki Iizuka, Hiromitsu Awano, Makoto Ikeda (UTokyo)
A deep neural network-based modeling attack for Double-Arbiter PUF (DAPUF) is proposed. Although DAPUF is known to be hi... [more] VLD2017-127
pp.231-236
RECONF 2015-06-20
11:10
Kyoto Kyoto University A Rapid Verification Environment for Statistical Evaluation of PUF Circuits
Toshihiro Katashita, Yasunori Onda, Yohei Hori (AIST)
In this study, we constructed a rapid experimentation environment for Physically Unclonable Function (PUF) circuit verif... [more] RECONF2015-18
pp.97-102
CAS, SIP, MSS, VLD, SIS [detail] 2014-07-11
15:10
Hokkaido Hokkaido University A distributed asynchronous arbiter for ring segmented bus type GALS systems
Yoshiki Odagiri, Masaki Akari (Okayama Prefectural Univ.), Masafumi Kondo (Kawasaki Univ. of Medical Welfare), Tomoyuki Yokogawa, Yoichiro Sato, Kazutami Arimoto (Okayama Prefectural Univ.)
A ring segmented bus (RSB) which connects the divided annular bus dynamically has been proposed for GALS systems. Howeve... [more] CAS2014-44 VLD2014-53 SIP2014-65 MSS2014-44 SIS2014-44
pp.237-242
EMM, ISEC, SITE, ICSS, IPSJ-CSEC, IPSJ-SPT [detail] 2013-07-18
14:50
Hokkaido   Evaluation Method for Arbiter PUF on FPGA and Its Vulnerability
Takanori Machida, Toshiki Nakasone, Kazuo Sakiyama (UEC)
Among Physical Unclonable Functions~(PUFs), Arbiter PUF is one of the delay-based PUFs that uses signal-delay time diffe... [more] ISEC2013-18 SITE2013-13 ICSS2013-23 EMM2013-20
pp.53-58
RECONF 2013-05-21
14:45
Kochi Kochi Prefectural Culture Hall Performance Evaluation of Physical Unclonable FUnctions on Kintex-7 FPGA
Yohei Hori, Toshihiro Katashita, Kazukuni Kobara (AIST)
The challenge-response properties of Physical Unclonable Functions (PUFs) on 28-nm process FPGA on the ten
SASEBO-GIII ... [more]
RECONF2013-17
pp.91-96
VLD, CAS, MSS, SIP 2012-07-02
13:40
Kyoto Kyoto Research Park An asynchronous tree arbiter with ability of concealing metastable operation duration time
Masafumi Kondo (Kawasaki Univ. of Medical Welfare), Kuniaki Ohyama, Yusuke Koyoshi, Tomoyuki Yokogawa, Yoichiro Sato (Okayama Prefectural Univ)
In recent years, an exclusive access to a shared bus and memory for multiple processor cores occurs in many computer sys... [more] CAS2012-9 VLD2012-19 SIP2012-41 MSS2012-9
pp.49-54
ICD 2011-12-15
13:00
Osaka   [Invited Talk] Tamper LSI Design Methodology using Physical Unclonable Function
Takeshi Fujino, Kota Furuhashi, Mitsuru Shiozaki (Ritsumeikan Univ.)
Physical Unclonable Functions (PUFs), which extract inherent ID from the device fluctuation, have been proposed as a new... [more] ICD2011-102
pp.13-18
IT 2011-07-21
15:15
Okayama Okayama University A study of statistical modeling of authentication using PUF
Satoru Ishii (Waseda Univ.), Takahiro Yoshida (Aoyama Univ.), Shunsuke Horii, Toshiyasu Matsushima (Waseda Univ.)
Nowadays, it is pointed out that storing the secret in nonvolatile memory of the device has a chance to leak the secret ... [more] IT2011-13
pp.19-24
VLD 2010-09-27
14:50
Kyoto Kyoto Institute of Technology Design and Evaluation of Arbiter Physical Unclonable Functions
Kota Furuhashi, Mitsuru Shiozaki, Akitaka Fukushima, Takahiko Murayama, Takeshi Fujino (Ritsumeikan Univ.)
Physical Unclonable Functions (PUF) have been proposed to produce tamper-resistant device or create unique ID of the sec... [more] VLD2010-44
pp.13-18
RECONF 2010-09-17
13:15
Shizuoka Shizuoka University (Faculty of Eng., Hall 2) Quantitative Performance Evaluation of Arbiter PUFs on FPGAs
Yohei Hori (AIST), Takahiro Yoshida (Chuo Univ.), Toshihiro Katashita, Akashi Satoh (AIST)
The quantitative performance indicators of Physical Unclonable
Functions (PUFs)---Randomness, Steadiness, Correctness,... [more]
RECONF2010-37
pp.115-120
CPSY 2007-12-19
13:00
Kyoto Campus Plaza Kyoto Evaluation of Switch Architecture Using Hybrid Structure of Crossbar and Arbiter under Variable Length Packet Environment
Takanori Mitsuno, Hiroaki Nishi (Keio Univ.)
New router architecture is required for achieving large-bandwidth and fine-grain communication to fill the needs of the ... [more] CPSY2007-41
pp.3-8
IN 2004-10-15
13:30
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Backbone router architecture for the next generation internet consisting of 100-Gbps mutifunctional network
Hiroaki Nishi (keio Univ.)
A router architecture for supporting the increasing internet traffic, called Tera-Gears, is discussed. Tera-Gears consis... [more] IN2004-90
pp.41-46
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