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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 9 of 9  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF 2023-08-04
16:25
Hokkaido Hakodate Arena
(Primary: On-site, Secondary: Online)
RECONF2023-18 (To be available after the conference date) [more] RECONF2023-18
pp.25-26
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-08
14:25
Kumamoto Kumamoto-Kenminkouryukan Parea CPSY2017-48 (To be available after the conference date) [more] CPSY2017-48
pp.69-74
SITE, EMM, ISEC, ICSS, IPSJ-CSEC, IPSJ-SPT [detail] 2017-07-15
14:15
Tokyo   Zynq-based Coprocessor Development Environment for Cryptography with Advanced Functionality and Its Evaluation
Takanori Miyoshi, Tsutomu Matsumoto (YNU) ISEC2017-37 SITE2017-29 ICSS2017-36 EMM2017-40
Bilinear pairing has a potential to produce a lot of new cryptographic protocols enabling advanced functionalities such ... [more] ISEC2017-37 SITE2017-29 ICSS2017-36 EMM2017-40
pp.275-280
CPSY, DC, IPSJ-ARC
(Joint) [detail]
2016-08-10
16:15
Nagano Kissei-Bunka-Hall (Matsumoto) Acceleration of the satellite engine simulation using Zynq
Ryotaro Sakai (Keio Univ.), Takaaki Miyajima (JAXA), Naru Sugimoto (Keio Univ.), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.) CPSY2016-36
(To be available after the conference date) [more] CPSY2016-36
pp.263-268
RCS, IT, SIP 2016-01-19
14:45
Osaka Kwansei Gakuin Univ. Osaka Umeda Campus Implementation of Digital Signal Processing Circuits in the Delta-Sigma Domain and its Application
Yasui Yuto, Hirano Satoshi, Goto Tomio, Sakurai Masaru (NIT) IT2015-99 SIP2015-113 RCS2015-331
We proposed a design method of signal processing circuits in the $DeltaSigma$ domain, which directly process signals mod... [more] IT2015-99 SIP2015-113 RCS2015-331
pp.279-284
ISEC 2015-12-18
13:55
Tokyo Kikai-Shinko-Kaikan Bldg. Evaluation of authenticated encryptions implemented on FPGA with high-level synthesis
Makoto Kotegawa, Keisuke Iwai, Hidema Tanaka, Takakazu Kurokawa (NDA) ISEC2015-55
Competition for Authenticated Encryption Security, Applicability, and Robustness (CAESAR) which is a development and eva... [more] ISEC2015-55
pp.9-16
CPSY, IPSJ-ARC 2015-10-08
10:00
Chiba Makuhari-messe [Poster Presentation] Evaluation of a Low Power CGRA EMAX Embedded with Zynq
Shohei Takeuchi, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) CPSY2015-51
We have been proposing EMAX (Energy-Aware Multimode Accelerator
Extension) that is one of CGRAs and can employ maximum ... [more]
CPSY2015-51
pp.39-41
RECONF 2015-09-18
14:30
Ehime Ehime University ZYNQ CLUSTER FOR CFD PARAMETRIC SURVEY
Naru Sugimoto, Hideharu Amano (Keio Univ.) RECONF2015-39
FaSTAR (Fast Aerodynamics Routines) is a state of the art CFD (Computational Fluid Dynamics) software package to enable ... [more] RECONF2015-39
pp.39-44
CPSY, DC, IPSJ-ARC
(Joint) [detail]
2015-08-04
14:00
Oita B-Con Plaza (Beppu) Evaluation of ARM-EMAX tightly coupled accelerator on Zynq
Shohei Takeuchi, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) CPSY2015-19
We focus on the data reusability of stencil computations on a previously proposed memory-network based accelerator, name... [more] CPSY2015-19
pp.47-52
 Results 1 - 9 of 9  /   
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