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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2024-02-28 13:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Study on Test Generation for Alleviating Over-testing of Approximate Multipliers Qilin Wang, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)  DC2023-97 |
In this study, we discuss the alleviation of over-testing for approximate circuits. We target a design of approximate mu... [more] | DC2023-97 pp.17-22 |
| EE, WPT (Joint) |
2023-10-06 10:00 |
Osaka | (Primary: On-site, Secondary: Online) |
Estimation of Energy Yield of a Solar Roof on EVs with Differential Power Processing Converter using a 3D Model and Validation of the Analytical Model Ryota Hiraide, Takumi Sugiura, Masatoshi Uno (Ibrarki Univ.) EE2023-19 |
Photovoltaic (PV) panels consist of a substring of multiple cells connected in series. In particular, the characteristic... [more] | EE2023-19 pp.11-16 |
| SCE | 2022-01-21 13:35 |
Online | Online | [Invited Talk]
Yield evaluation of adiabatic quantum-flux-parametron circuits using a planarized 10 kA/cm2 niobium process Taiki Yamae (Yokohama Natl. Univ./JSPS Research Fellow), Naoki Takeuchi, Nobuyuki Yoshikawa (Yokohama Natl. Univ.) SCE2021-12 |
Adiabatic quantum-flux-parametron (AQFP) logic is a superconducting logic family that can operate with low switching ene... [more] | SCE2021-12 pp.1-5 |
| US | 2020-09-28 16:20 |
Online | Online | Photoacoustic signal analyses from various chromophores Miya Ishihara, Takeshi Hirasawa, Kazuyoshi Tachi, Shinpei Okawa, Toshihiro Kushibiki, Akio Horiguchi (NDMC), Masato Sato (Tokai Univ.), Keiichi Ito (NDMC) US2020-39 |
Photoacoustic imaging is a method to visualize the distribution of optical absorbers, chromophore. Vascular imaging of h... [more] | US2020-39 pp.63-66 |
| HWS, VLD [detail] | 2020-03-04 14:55 |
Okinawa | Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
Gate Sizing for Programmable Delay Elements on Post-Silicon Delay Tuning Kota Muroi, Yukihide Kohira (UoA) VLD2019-103 HWS2019-76 |
Due to progressing process technology, yield of chips is reduced by timing violation caused by delay variation of gates ... [more] | VLD2019-103 HWS2019-76 pp.53-58 |
| ICTSSL, CAS | 2020-01-30 13:10 |
Tokyo | [Invited Talk]
A Proposal of MOS LSI Analog Sign-Off Verification. Kimihiro Ogawa (Success Inc.) CAS2019-70 ICTSSL2019-39 |
In analog MOS circuit sign-off verification to guarantee design yield, it is well known that analog oriented methodology... [more] | CAS2019-70 ICTSSL2019-39 pp.35-41 |
|
| IN, NS (Joint) |
2019-03-05 11:50 |
Okinawa | Okinawa Convention Center | Improve traffic state of low-priority vehicles by the yielding protocol using inter-vehicle communication in unsignalized crossroads Hayato Yajima, Kazumasa Takami (Soka Univ.) IN2018-124 |
Development of autonomous vehicles is progressing, and effects such as reduction of accidents and alleviation of congest... [more] | IN2018-124 pp.241-246 |
| WBS, ITS, RCC | 2018-12-07 09:30 |
Okinawa | Miyako Island Hirara Port Terminal Bldg. | Yielding Operation in Encounters with Emergency Vehicles and Analysis of Driver's Operation
-- The vehicle to vehicle communication and its problem toward automated driving cars -- Hideaki Nanba (Aichi-PU), Manabu Sawada (DENSO), Haruki Kawanaka, Koji Oguri (Aichi-PU) WBS2018-60 ITS2018-43 RCC2018-91 |
There are other difficult problems for the automated driving cars in the case of running on the public road. One of the ... [more] | WBS2018-60 ITS2018-43 RCC2018-91 pp.181-186 |
| VLD, HWS (Joint) |
2018-03-01 09:50 |
Okinawa | Okinawa Seinen Kaikan | Clustering for Reduction of Power Consumption and Area on Post-Silicon Delay Tuning Kota Muroi, Yukihide Kohira (Univ. of Aizu) VLD2017-107 |
Due to progressing process technology, yield of chips is reduced by timing violation caused by delay variation of gates ... [more] | VLD2017-107 pp.109-114 |
| SDM | 2017-10-26 09:30 |
Miyagi | Niche, Tohoku Univ. | [Invited Talk]
Utilization of Big Data for Innovation in Semiconductor Memory Manufacturing
-- Comprehensive Big-Data-Based Monitoring System for Yield Analysis in Semiconductor Manufacturing -- Hiroshi Akahori (Toshiba Memory), Kouta Nakata, Ryohei Orihara, Yoshiaki Mizuoka, Kentaro Takagi (Toshiba), Kenichi Kadota, Takaharu Nishimura, Yukako Tanaka, Hidetaka Eguchi (Toshiba Memory) SDM2017-55 |
In this work, we focus on yield analysis task where engineers identify the cause of failure from wafer failure map patte... [more] | SDM2017-55 pp.31-33 |
| US | 2017-07-27 09:45 |
Okayama | Technology for reducing paint-spatter in roller-coating Satoshi Ishida, Kenta Koike (NPHD) US2017-31 |
Paint-spatter in roller-coating is one of the important workability. Last year, we reported two factors (1.Spinnability ... [more] |
US2017-31 pp.5-9 |
|
| ICSS, IPSJ-SPT | 2017-03-13 14:25 |
Nagasaki | University of Nagasaki | Feature Extraction for Identifying High Yielding Investment Programs Related Transactions in Bitcoin Kentaroh Toyoda, Tomoaki Ohtsuki (Keio Univ.), P. Takis Mathiopoulos (UoA) ICSS2016-49 |
As recent research has revealed, Bitcoin is used as fraudulent activities such as HYIP (High Yield Investment Programs).... [more] | ICSS2016-49 pp.31-36 |
| VLD | 2017-03-01 14:50 |
Okinawa | Okinawa Seinen Kaikan | Post-Silicon Delay Tuning Method for Power Reduction considering Yield Improvement Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) VLD2016-104 |
Due to the progress of the process technology in LSI, the yield of chips is reduced by the timing violation because of t... [more] | VLD2016-104 pp.13-18 |
| US | 2016-07-29 16:35 |
Fukuoka | Chikushi Campus, Kyushu University | Development and application of new type viscometer Shujiro Mitani, Miki Hirano, Taichi Hirano, Keiji Sakai (UTokyo) US2016-37 |
The Electro-Magnetically Spinning (EMS) method is a novel technique for measuring shear viscosity of liquid. Typical typ... [more] | US2016-37 pp.27-29 |
| VLD | 2016-03-01 17:30 |
Okinawa | Okinawa Seinen Kaikan | [Memorial Lecture]
A Closed-Form Stability Model for Cross-Coupled Inverters Operating in Sub-Threshold Voltage Region Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.) VLD2015-131 |
A cross-coupled inverter which is an essential element of on-chip memory subsystems plays an important role in synchrono... [more] | VLD2015-131 p.117 |
| SCE | 2016-01-21 13:25 |
Tokyo | Yield evaluation of 40k gate-scale adiabatic-quantum-flux-parametron circuits Tatsuya Narama, Naoki Takeuchi (Yokohama National Univ.), Thomas Ortlepp (CiS), Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.) SCE2015-42 |
We are studying adiabatic quantum flux parametron (AQFP) circuit, which is very energy-efficient superconductor logic. R... [more] | SCE2015-42 pp.35-40 |
|
| ICD, CPSY | 2015-12-18 15:55 |
Kyoto | Kyoto Institute of Technology | Performance Analysis of Analog to Digital Converter Based on Stochastic Comparator Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada (Tokyo University) ICD2015-93 CPSY2015-106 |
A performance model for Analog to Digital Converter (ADC) based on stochastic comparator has been proposed by analyzing ... [more] | ICD2015-93 CPSY2015-106 pp.123-128 |
| SDM, ICD | 2015-08-24 10:20 |
Kumamoto | Kumamoto City | Development of a compacted doubly nesting array in Narrow Scribe Line aimed at detecting soft failures of interconnect via Hiroki Shinkawata, Nobuo Tsuboi (REL), Atsushi Tsuda (RSD), Shingo Sato (Kansai), Yasuo Yamaguchi (REL) SDM2015-58 ICD2015-27 |
We introduce a new addressable test structure array using for mass production stage which is compacted doubly nesting ar... [more] | SDM2015-58 ICD2015-27 pp.7-10 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 14:05 |
Kagoshima | A Heuristic Design Method for Yield Improvement based on PPCs Shunichi Sanae, Yuko Hara-Azumi (NAIST), Shigeru Yamashita (Ritsumeikan Univ.), Yasuhiko Nakashima (NAIST) VLD2013-65 DC2013-31 |
A PPC (Partially-Programmable Circuit) is a novel circuit model, which replaces some logic gates with LUTs (Look Up Tabl... [more] | VLD2013-65 DC2013-31 pp.27-32 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 13:45 |
Kagoshima | A Tuning Method of Programmable Delay Element with an Ordered Finite Set of Delay Values for Yield Improvement Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) VLD2013-99 DC2013-65 |
Due to progressing the process technology in LSI, the yield of LSI chips is reduced by timing violations caused by delay... [more] | VLD2013-99 DC2013-65 pp.275-280 |
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