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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, CAS, MSS, SIP 2016-06-17
15:10
Aomori Hirosaki Shiritsu Kanko-kan Clock Distribution Network with Multiple Source Buffers for Stacked Chips
Nanako Niioka, Masashi Imai, Kaoru Furumi, Atsushi Kurokawa (Hirosaki Univ.) CAS2016-31 VLD2016-37 SIP2016-65 MSS2016-31
In this report, we present a method to reduce clock skew among stacked chips by a clock distribution network with multip... [more] CAS2016-31 VLD2016-37 SIP2016-65 MSS2016-31
pp.167-172
VLD, CAS, MSS, SIP 2016-06-17
15:30
Aomori Hirosaki Shiritsu Kanko-kan Thermal Analysis in 3D ICs
Kaoru Furumi, Masashi Imai, Nanako Niioka, Atsushi Kurokawa (Hirosaki Univ.) CAS2016-32 VLD2016-38 SIP2016-66 MSS2016-32
Three-dimensional integrated circuits (3D ICs) lead to higher power densities than 2D ICs because of the stacking of mul... [more] CAS2016-32 VLD2016-38 SIP2016-66 MSS2016-32
pp.173-178
EMCJ 2004-10-01
11:20
Nara   Shielded via structures for high-speed printed circuit boards
Taras Kushta, Kaoru Narita (NEC)
Shielded via structures formed by signal and ground vias jointly are an important type of vertical transitions providing... [more] EMCJ2004-60
pp.29-34
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