Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
ICD, CPSY |
2016-12-16 14:20 |
Tokyo |
Tokyo Institute of Technology |
[Invited Talk]
A Data-Driven Processor Realizing Trillion Sensors Universe Hiroaki Nishikawa (Univ. of Tsukuba) ICD2016-96 CPSY2016-102 |
This paper introduces a data-driven processor aiming at realizing Trillion Sensors Universe. Execution control scheme in... [more] |
ICD2016-96 CPSY2016-102 pp.139-144 |
RECONF |
2014-06-12 10:50 |
Miyagi |
Katahira Sakura Hall |
An Asynchronous High-Performance FPGA Based on LEDR/Four-Phase-Dual-Rail Hybrid Architecture Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) RECONF2014-6 |
This paper presents an asynchronous high-performance FPGA that combines Four-Phase Dual-Rail (FPDR) protocol and Level-E... [more] |
RECONF2014-6 pp.27-30 |
IE, ICD, VLD, IPSJ-SLDM [detail] |
2013-10-07 16:05 |
Aomori |
|
A 2.4x-Real-Time VLSI Processor for 60-kWord Continuous Speech Recognition Guangji He, Yuki Miyamoto, Kumpei Matsuda, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ) VLD2013-52 ICD2013-76 IE2013-52 |
This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous speech recognition based on a co... [more] |
VLD2013-52 ICD2013-76 IE2013-52 pp.29-34 |
IE, ICD, VLD, IPSJ-SLDM [detail] |
2013-10-08 10:35 |
Aomori |
|
New Architecture for Multiple-Valued Fine-Grain Reconfigurable VLSI Based on Current-Mode Logic Xu Bai, Michitaka Kameyama (Tohoku Univ.) VLD2013-57 ICD2013-81 IE2013-57 |
This article presents a fine-grain reconfigurable VLSI based on multiple-valued X-net data transfer scheme. Two binary d... [more] |
VLD2013-57 ICD2013-81 IE2013-57 pp.59-64 |
SIS |
2013-06-13 14:55 |
Kagoshima |
Houzan Hall (Kagoshima) |
VLSI Design of Transform and Quantization Units in Scalable Distributed Video Coding Narumi Tanaka, Masashi Okada (Osaka Univ), Kazuhito Sakomizu (Osaka Univ/OKI), Takao Onoye (Osaka Univ) SIS2013-8 |
In this research, we aim to realize an embedded system for distributed video coding (DVC) encoder. Since transform and q... [more] |
SIS2013-8 pp.39-44 |
ICD, IPSJ-ARC |
2012-01-20 15:10 |
Tokyo |
|
An Evaluation of An FPGA Based on Synchronous/Asynchronous Hybrid Architecture Yoshiya Komatsu, Masanori Hariyama, Shota Ishihara, Ryoto Tsuchiya, Michitaka Kameyama (Tohoku Univ.) ICD2011-142 |
This paper presents an FPGA architecture that combines synchronous and asynchronous architectures. Datapath components s... [more] |
ICD2011-142 pp.93-96 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 10:05 |
Miyazaki |
NewWelCity Miyazaki |
A 40nm 144mW VLSI Processor for Realtime 60k Word Continuous Speech Reconginion Takanobu Sugahara, Guangji He, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) CPM2011-164 ICD2011-96 |
We have developed a low power VLSI chip for 60k-word real-time continuous speech recognition based on HMM(Hidden Markov ... [more] |
CPM2011-164 ICD2011-96 pp.79-84 |
ICD, IE, SIP, IPSJ-SLDM [detail] |
2011-10-24 14:45 |
Miyagi |
Ichinobo(Sendai) |
Architecture of a Dynamically Reconfigurable VLSI Processor Based on Register-Transfer-Level Packet Transfer Yoshichika Fujioka (Hachinohe Inst. of Tech.), Sho Takizawa, Michitaka Kameyama (Tohoku Univ.) SIP2011-64 ICD2011-67 IE2011-63 |
Register-transfer-level packet routing scheme is proposed for intra-chip data transfer to make the size of configuration... [more] |
SIP2011-64 ICD2011-67 IE2011-63 pp.13-18 |
SIS |
2010-12-02 15:15 |
Nara |
|
Circuit Design of a 128-point FFT Processor Using Pipeline MDC Architecture for 8x8 MIMO-OFDM Receivers Atsushi Orikasa, Yoshikazu Miyanaga, Shingo Yoshizawa (Hokkaido Univ.) SIS2010-45 |
This report presents a VLSI architecture of 128-point FFT in a 8x8 MIMO-OFDM receiver. A pipeline FFT processor based on... [more] |
SIS2010-45 pp.59-64 |
RECONF |
2010-09-17 10:15 |
Shizuoka |
Shizuoka University (Faculty of Eng., Hall 2) |
Structure of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture Shota Ishihara, Ryoto Tsuchiya, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) RECONF2010-33 |
Asynchronous circuit is power-efficient for low-workload sub-circuits since there is no power consumption of the clock t... [more] |
RECONF2010-33 pp.91-95 |
SIS |
2010-06-10 11:10 |
Hokkaido |
Abashiri Public Auditorium |
LSI Design of a Pipelined MMSE Detector Using Strassen Algorithm for 8x8 MIMO-OFDM Receiver Daisuke Nakagawa, Shingo Yoshizawa, Yoshikazu Miyanaga (Hokkaido Univ) SIS2010-4 |
This report presents a piplined MMSE detection using Strassen's algorithms of matrix inversion and multiplication in a 8... [more] |
SIS2010-4 pp.19-24 |
IPSJ-SLDM, VLD, CPSY, RECONF [detail] |
2010-01-27 09:00 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
Architecture of a Low-Power FPGA Based on Self-Adaptive Voltage Control Shota Ishihara, Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) VLD2009-84 CPSY2009-66 RECONF2009-69 |
This paper presents a low-power FPGA with multiple supply voltages. In the proposed FPGA, the supply voltage of each log... [more] |
VLD2009-84 CPSY2009-66 RECONF2009-69 pp.95-99 |
ICD |
2009-12-14 13:30 |
Shizuoka |
Shizuoka University (Hamamatsu) |
[Poster Presentation]
Development of a Stream Cipher Engine Chip Takumi Ishihara, Harunobu Uchiumi, Yusuke Osumi, Masa-aki Fukase, Tomoaki Sato (Hirosaki Univ.) ICD2009-94 |
One of crucial points for next generation ubiquitous network is to keep the temporary security without relying on perman... [more] |
ICD2009-94 pp.95-100 |
ICD |
2009-12-15 10:00 |
Shizuoka |
Shizuoka University (Hamamatsu) |
[Invited Talk]
A New VLSI System Architecture Mimicking the Processing in the Mind Tadashi Shibata (Univ. of Tokyo.) ICD2009-95 |
The performance of a today’s computer is really marvelous. It can carry out a prodigious amount of numerical calculation... [more] |
ICD2009-95 pp.101-109 |
RECONF |
2009-09-18 13:35 |
Tochigi |
Utsunomiya Univ. |
An Asynchronous FPGA Using LEDR/4-Phase-Dual-Rail Protocol Converters Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) RECONF2009-36 |
This paper presents an asynchronous FPGA that combines the 4-phase dual-rail encoding and the Level-Encoded Dual-Rail (L... [more] |
RECONF2009-36 pp.103-108 |
CPM |
2009-08-11 14:20 |
Aomori |
Hirosaki Univ. |
Development of a Stream Cipher Engine Takumi Ishihara, Harunobu Uchiumi, Yusuke Osumi, Masa-aki Fukase, Tomoaki Sato (Hirosaki Univ.) CPM2009-49 |
One of crucial points for ubiquitous network is to keep the temporary security without relying on permanent network infr... [more] |
CPM2009-49 pp.83-88 |
SIS |
2009-06-12 10:35 |
Okinawa |
|
VLSI Design of a Dynamic Reconfigurable MMSE Detector for 4x4 MIMO-OFDM Receiver Hirokazu Ikeuchi, Shingo Yoshizawa, Yoshikazu Miyanaga (Hokkaido Univ.) SIS2009-14 |
This report presents a VLSI architecture of dynamic reconfigurable MMSE detection in a 4x4 MIMO-OFDM receiver. MIMO-OFDM... [more] |
SIS2009-14 pp.79-84 |
VLD |
2009-03-12 17:05 |
Okinawa |
|
Transform and Quantization Architecture with All-Zero Detection and Bit Estimation for H.264/AVC Hiroki Kuniyasu, Tomoyuki Kishida, Tian Song, Takashi Shimamoto (Tokushima Univ.) VLD2008-154 |
H.264/AVC introduced a certain numbers of novel prediction modes compared to the previous standards. Rate-Distortion Opt... [more] |
VLD2008-154 pp.165-170 |
SIS |
2008-06-12 14:25 |
Hokkaido |
|
VLSI Architecture of a Pipelined MMSE Detector in a 4x4 MIMO-OFDM Receiver Shingo Yoshizawa, Yoshikazu Miyanaga (Hokkaido Univ.) SIS2008-9 |
This report presents a VLSI architecture of MMSE detection in a 4x4 MIMO-OFDM receiver. Packet-based MIMO-OFDM imposes a... [more] |
SIS2008-9 pp.47-52 |
SIS |
2007-12-11 10:15 |
Hyogo |
|
JPEG 2000 Codec LSI for Low Delay Image Transmission System Yusuke Inoie, Ryoichi Inada, Takafumi Kasuga, Masayuki Miyama (Kanazawa Univ.), Masashi Nakao (EIZO NANAO Corp.), Yoshio Matsuda (Kanazawa Univ.) SIS2007-59 |
This paper describes a JPEG 2000 codec LSI used low delay and high resolution image transmission system. In EBCOT proces... [more] |
SIS2007-59 pp.7-12 |