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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD 2009-03-11
10:30		 Okinawa   Optimum Code Scheduling for VLIW DSP SPXK5 considering Conditional Execution
Tetsuya Yamamoto, Nagisa Ishiura (Kwansei Gakuin Univ.), Takahiro Kumura, Masao Ikekawa (NEC), Masaharu Imai (Osaka Univ.) VLD2008-126		 This article presents an optimum code scheduling method for digital signal processor SPXK5 taking account of its archite... [more] VLD2008-126
pp.1-6
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]		 2007-11-22
14:55		 Fukuoka Kitakyushu International Conference Center Cycle Partitioned Scheduling for Code Optimization of VLIW DSP
Yuuki Masui, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2007-102 DC2007-57		 This paper proposes a cycle partitioned scheduling method for code optimization of VLIW DSPs. The previously proposed op... [more] VLD2007-102 DC2007-57
pp.79-84
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