Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD |
2016-03-01 11:20 |
Okinawa |
Okinawa Seinen Kaikan |
Timing-error-tolerant AES Cipher Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-123 |
With the technologies advance, the importance of crypto circuits is increasing as well. AES cipher is well known as theo... [more] |
VLD2015-123 pp.73-78 |
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] |
2016-01-21 13:25 |
Kanagawa |
Hiyoshi Campus, Keio University |
A floorplan-driven high-level synthesis algorithm resilient to dynamic delay variations Koki Igawa, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-105 CPSY2015-137 RECONF2015-87 |
Recently, we have proposed a multi-scenario high-level synthesis algorithm targeting static process variations. The algo... [more] |
VLD2015-105 CPSY2015-137 RECONF2015-87 pp.209-214 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 12:05 |
Nagasaki |
Nagasaki Kinro Fukushi Kaikan |
A Data-dependent Approximation-circuit Design using Timing-error Prediction Scheme and its Evaluations on FPGA Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-66 DC2015-62 |
The propagation delay and the transition probability along each path inside an LSI widely vary depending on input data, ... [more] |
VLD2015-66 DC2015-62 pp.183-188 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 09:40 |
Oita |
B-ConPlaza |
Data Dependent Optimization using Suspicious Timing Error Prediction for Reconfigurable Approximation Circuits Kazushi Kawamura, Shin-ya Abe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-80 DC2014-34 |
The propagation delay along each path inside an LSI widely varies depending on input data, and this property can be expl... [more] |
VLD2014-80 DC2014-34 pp.51-56 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 10:05 |
Oita |
B-ConPlaza |
An Effective Robust Design Using Improved Checkpoint Insertion Algorithm for Suspicious Timing-Error Prediction Scheme and its Evaluations Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-81 DC2014-35 |
As process technologies advance, process and delay variation causes a complex timing design and in-situ timing error cor... [more] |
VLD2014-81 DC2014-35 pp.57-62 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 14:55 |
Kagoshima |
|
Suspicious timing error prediction using check points Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-67 DC2013-33 |
Due to advance process technologies, timing design of LSIs has become more difficult and the importance of timing error ... [more] |
VLD2013-67 DC2013-33 pp.39-44 |
NS, RCS (Joint) |
2010-12-17 13:40 |
Okayama |
Okayama Univ. |
Performance Evaluation of Transmission Timing Control Using Mobility Prediction in Opportunistic Roadside-to-Vehicle Communication Ryo Aoki, Hiroyuki Kubo, Ryoichi Shinkuma, Tatsuro Takahashi (Kyoto Univ) NS2010-136 |
The rapid advance in wireless communication has brought about high-speed and location-free access to content. However, t... [more] |
NS2010-136 pp.185-190 |
SP |
2008-10-23 17:00 |
Kumamoto |
Kumamoto Univ. |
Model-based duration analysis on English natives and Thai learners Chatchawarn Hansakunbuntheung (Waseda Univ.), Hiroaki Kato (ATR), Yoshinori Sagisaka (Waseda Univ.) SP2008-62 |
This paper presents an English timing evaluation method to characterize English timing of Thai-native English learners. ... [more] |
SP2008-62 pp.37-40 |