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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD, HWS | 2023-10-31 14:20 |
Mie | (Primary: On-site, Secondary: Online) |
Evaluation of Time-to-Digital Converter in Laser Fault Injection Detection on FPGA Shungo Hayashi, Junichi Sakamoto (YNU/AIST), Masaki Chikano, Tsutomu Matsumoto (YNU)  HWS2023-56 ICD2023-35 |
Fault injection attacks are attacks that intentionally introduce faults into a running device in order to expose interna... [more] | HWS2023-56 ICD2023-35 pp.10-15 |
| DC | 2017-12-15 15:30 |
Akita | Akita Study Center, The Open University of Japan | A Test Clock Observation Method Using Time-to-Digital Converters for Built-In Self-Test in FPGAs Yousuke Miyake, Yasuo Sato, Seiji Kajihara (KIT) DC2017-75 |
A delay measurement method combining a logic BIST with a variable test clock has been proposed to improve field reliabil... [more] | DC2017-75 pp.37-42 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-30 09:25 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Design of TDC Embedded in Scan FFs for Testing Small Delay Faults Shingo Kawatsuka, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2016-62 DC2016-56 |
With improvement of semiconductor manufacturing process, small delay becomes more important cause of timing failures. ... [more] |
VLD2016-62 DC2016-56 pp.105-110 |
| CAS, NLP | 2016-10-27 15:25 |
Tokyo | Self-Calibration and Trigger Circuit for 2-Step SAR TDC Takashi Ida, Yuki Ozawa, Richen Jiang, Haruo Kobayashi (Gunma Univ.), Ryoji Shiota (socionext) CAS2016-48 NLP2016-74 |
This paper presents a 2-step successive-approximation-register time-to-digital converter (SAR TDC) architecture with its... [more] | CAS2016-48 NLP2016-74 pp.55-60 |
|
| ICD, SDM, ITE-IST [detail] | 2016-08-01 10:25 |
Osaka | Central Electric Club | A Low-Power Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Charge-Pump and SAR ADC Anugerah Firdauzi, Zule Xu, Masaya Miyahara, Akira Matsuzawa (Tokyo Tech.) SDM2016-50 ICD2016-18 |
This paper presents a time-to-digital converter (TDC) using delta-sigma architecture which utilizes a charge pump as the... [more] | SDM2016-50 ICD2016-18 pp.9-14 |
| ICD, CPSY | 2014-12-01 12:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Time-to-Digital Converters with Delta-Sigma Modulation
-- Key Component of Time-Domain Analog Circuitry -- Haruo Kobayashi (Gunma Univ.) ICD2014-75 CPSY2014-87 |
This paper presents the research results of delta-sigma time-to-digital converters (TDCs) performed at the author’s labo... [more] | ICD2014-75 CPSY2014-87 pp.13-18 |
| SDM, ICD | 2013-08-02 11:15 |
Ishikawa | Kanazawa University | [Invited Talk]
An LDPC Decoder with Time Domain Analog and Digital Mixed Signal Processing Daisuke Miyashita, Ryo Yamaki (Toshiba), Kazunori Hashiyoshi (Toshiba Microelectronics), Hiroyuki Kobayashi, Shouhei Kousai, Yukihito Oowaki, Yasuo Unekawa (Toshiba) SDM2013-79 ICD2013-61 |
Analog computation is potentially more efficient in certain arithmetic operations since a single wire can represent mult... [more] | SDM2013-79 ICD2013-61 pp.71-76 |
| ICD, ITE-IST | 2010-07-22 15:50 |
Osaka | Josho Gakuen Osaka Center | [Invited Talk]
A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer with a Time-Windowed Time-to-Digital Converter Tadashi Maeda, Takashi Tokairin (Renesas Electronics Corporation), Masaki Kitsunezuka (NEC Corp.), Mitsuji Okada (Renesas Electronics Corporation), Muneo Fukaishi (NEC Corp.) ICD2010-29 |
A 2.1-to-2.8-GHz low-power consumption all-digital phase locked loop (ADPLL) with a time-windowed time-to-digital conver... [more] | ICD2010-29 pp.49-54 |
| SCE | 2005-10-14 15:20 |
Aichi | Nagoya Univ. | Quantitative evaluation of timing jitter for SFQ circuits Masayoshi Terabe (Nagoya Univ.), Akito Sekiya (CREST-JST), Akira Fujimaki (Nagoya Univ.) |
We measured the timing jitter of Josephson transmission lines with the time-to-digital converter (TDC) which can detect ... [more] | SCE2005-22 pp.25-30 |
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