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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2024-02-28 13:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Test Point Selection Method for Multi-Cycle BIST Using Deep Reinforcement Learning Kohei Shiotani, Tatsuya Nishikawa, Shaoqi Wei, Senling Wang, Hiroshi Kai, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.)  DC2023-98 |
Multi-cycle BIST is a test method that performs multiple captures for each scan pattern, proving effective in reducing t... [more] | DC2023-98 pp.23-28 |
| ICSS | 2020-11-26 16:00 |
Online | Online | Non-interactive oblivious transfer protocol based on TEE Masahide Kobayashi, Takashi Nishide (Univ. of Tsukuba) ICSS2020-24 |
Oblivious transfer is a protocol consisting of two parties, a data sender and receiver, and is used for secure computati... [more] | ICSS2020-24 pp.26-31 |
| VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-14 15:20 |
Ehime | Ehime Prefecture Gender Equality Center | A Generation Method of Easily Testable Functional k Time Expansion Model for a Transition Fault Model Using Controller Augmentation and Partial Scan Designs Yuta Ishiyama, Toshinori Hosokawa, Yuki Ikegaya (Nihon Univ.) VLD2019-43 DC2019-67 |
One of the challenges on VLSI testing is to reduce the area overhead and test application time of design-for-testability... [more] | VLD2019-43 DC2019-67 pp.133-138 |
| DC | 2019-02-27 14:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Compaction Method for Test Sensitization State in Controllers Yuki Ikegaya, Yuta Ishiyama, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.) DC2018-80 |
One of the challenges on VLSI testing is to reduce the area overhead of design-for-testability and to increase the fault... [more] | DC2018-80 pp.55-60 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 14:30 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | A Method of LFSR Seed Generation for Improving Quality of Delay Fault BIST Kyonosuke Watanabe, Satoshi Ohtake (Oita Univ.) VLD2017-35 DC2017-41 |
With the miniaturization and high speed of large scale integrated circuits, it has become important to test delay faults... [more] | VLD2017-35 DC2017-41 pp.49-54 |
| KBSE | 2017-03-03 12:50 |
Ishikawa | KBSE2016-40 |
Self-adaptive systems, which change their behaviors to adapt to their environmental changes, are focused on in recent ye... [more] | KBSE2016-40 pp.7-12 |
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| DC | 2017-02-21 14:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An Untestable Fault Identification Method for Sequential Circuits Based on SAT Using Unreachable States Morito Niseki, Toshinori Hosokawa (Nihon Univ.), Msayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) DC2016-79 |
Scan design has problems such as large hardware overhead and long test application time. Non-scan based test generation ... [more] | DC2016-79 pp.29-34 |
| DC | 2016-06-20 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Binding Method for Testability to Generate Easily Testable Functional Time Expansion Models Mamoru Sato, Toshinori hosokawa, Tetsuya Masuda, Jun Nishimaki (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2016-14 |
A test generation method for datapaths using easily testable functional time expansion models was proposed as efficient ... [more] | DC2016-14 pp.25-30 |
| DC | 2015-02-13 15:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg | A Method of LFSR Seed Generation for Hierarchical BIST Kosuke Sawaki, Satoshi Ohtake (Oita Univ.) DC2014-85 |
A linear feedback shift register (LFSR) is used as a test pattern generator of built-in self-test (BIST). In BIST, alth... [more] |
DC2014-85 pp.43-48 |
| DC | 2014-06-20 16:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An evaluation for Testability of Functional k-Time Expansion Models Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2014-17 |
A test generation method using functional k-time expansion models for data paths was proposed. In the test generation m... [more] |
DC2014-17 pp.45-50 |
| DC | 2013-06-21 13:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Controller Augmentation Method to Generate Functional k-Time Expansion Models for Data Path Circuits Yusuke Kodama, Jun Nishimaki, Tetsuya Masuda, Toshinori Hosokawa (Nihon Univ), Hideo Fujiwara (Osaka Gakuin Univ) DC2013-10 |
In recent years, various high-level test synthesis methods for LSIs have been proposed for the improvement in design pro... [more] | DC2013-10 pp.1-6 |
| NC, NLP | 2013-01-24 14:30 |
Hokkaido | Hokkaido University Centennial Memory Hall | Calculating finite-time Lyapunov exponents in time delayed dynamical systems Kazutaka Kanno, Atsushi Uchida (Saitama Univ.) NLP2012-116 NC2012-106 |
Lyapunov exponents represents a exponential expansion (construction) rate of a in nitesimal perturbation to an orbit of ... [more] | NLP2012-116 NC2012-106 pp.73-78 |
| DC | 2011-02-14 14:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Test Generation Method for Datapath Circuits Using Functional Time Expansion Models Teppei Hayakawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.) DC2010-65 |
Some large-scale integrated circuits have been recently designed at high-level by behavioral descriptions. Behavioral sy... [more] | DC2010-65 pp.39-44 |
| DC | 2010-06-25 14:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Class of Partial Thru Testable Sequential Circuits with Multiplexers Nobuya Oka, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2010-9 |
Partially thru testable sequential circuits are known to be practically testable, and a condition for the testable seque... [more] | DC2010-9 pp.7-11 |
| DC | 2010-02-15 10:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Study on a Test Generation Method for Transition Faults Using Multi Cycle Capture Test Hiroshi Ogawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyusyu Univ.), Koji Yamazaki (Meiji Univ.) DC2009-67 |
Overtesting induces unnecessary yield loss. Untestable faults have no effect on normal functions of circuits. However, i... [more] | DC2009-67 pp.13-18 |
| VLD, IPSJ-SLDM | 2009-05-20 15:20 |
Fukuoka | Kitakyushu International Conference Center | A scan test generation method to reduce the number of detected untestable faults Hiroshi Ogawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.), Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.) VLD2009-3 |
There are faults which can be detected by only the invalid test patterns. This is one of the causes for the overtesting.... [more] | VLD2009-3 pp.13-18 |
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