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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM | 2019-02-07 11:25 |
Tokyo | [Invited Talk]
Ultrafine 3D Interconnect Technology Using Directed Self-Assembly Takafumi Fukushima, Murugesan Mariappan, Mitsumasa Koyanagi (Tohoku Univ.)  SDM2018-92 |
A directed self-assembly (DSA) technology is applied to fabricate ultrafine pitch TSV (Through-Silicon Vias) for ultra-h... [more] | SDM2018-92 pp.5-8 |
|
| SDM | 2019-02-07 13:10 |
Tokyo | [Invited Talk]
Stress Investigation of Annular-Trench-Isolated (ATI) Through Silicon Via (TSV) Wei Feng, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi (AIST) SDM2018-93 |
The methods as parylene substitute of SiO2 as dielectric layer and annular structure lose efficacy for thermal stress re... [more] | SDM2018-93 pp.9-14 |
|
| EMCJ, IEE-EMC, IEE-MAG | 2018-11-22 14:20 |
Overseas | KAIST | A Novel Eye-Diagram Estimation Method for Pulse Amplitude Modulation with N-level on Stacked Through Silicon Vias Junyong Park, Youngwoo Kim, Kyungjun Cho, Seongsoo Lee, Joungho Kim (KAIST) EMCJ2018-64 |
This paper proposed an eye-diagram estimation method for pulse amplitude modulation with N-level signaling. For verifica... [more] | EMCJ2018-64 p.29 |
| VLD, CAS, MSS, SIP | 2016-06-17 15:30 |
Aomori | Hirosaki Shiritsu Kanko-kan | Thermal Analysis in 3D ICs Kaoru Furumi, Masashi Imai, Nanako Niioka, Atsushi Kurokawa (Hirosaki Univ.) CAS2016-32 VLD2016-38 SIP2016-66 MSS2016-32 |
Three-dimensional integrated circuits (3D ICs) lead to higher power densities than 2D ICs because of the stacking of mul... [more] | CAS2016-32 VLD2016-38 SIP2016-66 MSS2016-32 pp.173-178 |
| EMCJ, IEE-EMC, IEE-MAG | 2016-06-02 16:10 |
Overseas | NTU, Taiwan | [Invited Talk]
Modeling and Measuring Vertical Interconnects with Impedance Control Over a Wide Frequency Range Kuan-Chung Lu, Tzyy-Sheng Horng (National Sun Yat-sen Univ.) EMCJ2016-35 |
The advantages of vertical interconnects include superior electrical transmissions for stacked dies, higher I/O density,... [more] | EMCJ2016-35 pp.57-62 |
| SDM, ICD | 2013-08-01 13:45 |
Ishikawa | Kanazawa University | [Invited Talk]
Design and diagnosis of 100GB/s Wide I/O with 4096b TSVs through Active Silicon Interposer Makoto Nagata, Satoshi Takaya (Kobe Univ.), Hiroaki Ikeda (ASET) SDM2013-71 ICD2013-53 |
A 4096-bit wide I/O bus structure is designed and demonstrated with a three dimensional chip stack incorporating memory,... [more] | SDM2013-71 ICD2013-53 pp.31-34 |
| CPM | 2010-07-30 09:30 |
Hokkaido | Michino-Eki Shari Meeting Room | Low temperature of deposition of ZrNx film using radical reaction Masaru Sato, Mayumi B. Takeyama (kitami Inst. of Tech.), Yuichiro Hayasaka, Eiji Aoyagi (Tohoku Univ.), Atsushi Noya (kitami Inst. of Tech.) CPM2010-36 |
Recently, an increase in the integration density of the Si-ULSI system is realized in the 3-D packaging technology. A t... [more] |
CPM2010-36 pp.29-34 |
| SDM | 2009-10-29 15:30 |
Miyagi | Tohoku University | Silicon Wafer Thinning Technology for Three-Dimensional Integrated Circuit by Wet Etching Kazuhiro Yoshikawa, Tomotsugu Ohashi, Tatsuro Yoshida, Takenao Nemoto, Tadahiro Ohmi (Tohoku Univ.) SDM2009-120 |
A three-dimensional integrated circuit is developed as an emerging technology in a semiconductor industry. The silicon w... [more] | SDM2009-120 pp.15-19 |
| CPM | 2009-08-11 11:15 |
Aomori | Hirosaki Univ. | Effectiveness of New Deposition Method for Barrier Metal Applicable to Through Silicon Via
-- Properties of ZrNx Film Formed at Low Temperature -- Masaru Sato, Mayumi B. Takeyama (Kitami Inst. of Tech.), Yuichiro Hayasaka, Eiji Aoyagi (Tohoku Univ.), Atsushi Noya (Kitami Inst. of Tech.) CPM2009-44 |
A low process temperature as low as 200°C is one of the most important requirements for the metallization technology of ... [more] | CPM2009-44 pp.57-60 |
| ED | 2009-07-31 11:15 |
Osaka | Osaka Univ. Icho-Kaikan | Study of Electroless Copper Plating for Through Si Via Filling Fumihiro Inoue, Takumi Yokoyama (Kansai Univ.), Kazuhiro Yamamoto, Shukichi Tanaka (NiCT), Shoso Shingubara (Kansai Univ.) ED2009-111 |
In recent studies, The formation of through-Silicon via hole (TSV) which stacks multiple layers of thin Si substrates is... [more] | ED2009-111 pp.47-50 |
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