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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 34  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM 2021-10-21
15:20
Online Online Highly sensitive TMR sensor and its application to bio-magnetic field measurement
Mikihiko Oogane (Tohoku Univ.) SDM2021-50
The tunnel magneto-resistive sensor (TMR sensor) using a ferromagnetic tunnel junction with small size and low power con... [more] SDM2021-50
pp.21-22
IE, IMQ, MVE, CQ
(Joint) [detail]
2020-03-05
11:10
Fukuoka Kyushu Institute of Technology
(Cancelled but technical report was issued)
Human Motion Recognition from Single Camera Images Using TMRI
Cao Jing, Youtaro Yamashita, Joo Kooi Tan (Kyutech) IMQ2019-17 IE2019-99 MVE2019-38
In recent years, research on computer vision has progressed and is being applied in a wide range of fields. Among them, ... [more] IMQ2019-17 IE2019-99 MVE2019-38
pp.17-21
CPSY, DC, IPSJ-ARC
(Joint) [detail]
2017-07-26
14:00
Akita Akita Atorion-Building (Akita) A Study on Implementation Method of Byzantine Fault Tolerant Systems
Takeru Nanao, Yudai Ishikawa, Masashi Imai (Hirosaki Univ.) DC2017-17
A fault tolerant system does not cause a failure even if a fault occurs. The algorithm OM has been proposed as a basic B... [more] DC2017-17
pp.7-12
ICD 2017-04-20
11:00
Tokyo   [Invited Talk] A 4Gb LPDDR2 STT-MRAM with Compact 9F2 1T1MTJ Cell and Hierarchical Bitline Architecture
Kenji Tsuchida (Toshiba), Kwangmyoung Rho, Dongkeun Kim (SK hynix), Yutaka Shirai (Toshiba), Jihyae Bae (SK hynix), Tsuneo Inaba, Hiromi Noro (Toshiba), Hyunin Moon, Sungwoong Chung (SK hynix), Kazumasa Sunouchi (Toshiba), Jinwon Park, Kiseon Park (SK hynix), Akihito Yamamoto (Toshiba), Seoungju Chung, Hyeongon Kim (SK hynix) ICD2017-3
The experimental 4-Gbit STT-MRAM with 9F2 1T1MTJ cell of 90nm by 90nm is presented. Hierarchical bit line architecture a... [more] ICD2017-3
pp.11-16
MVE, IE, CQ, IMQ
(Joint) [detail]
2017-03-07
14:55
Fukuoka Kyusyu Univ. Ohashi Campus Proposal and evaluation measurement method of three-dimensional position in the wide area by TMR high-precision magnetic tracking
Ryunosuke Morimoto, Shun'ichi Tano, Tomonori Hashiyama (UEC), Mitsuru Iwata (TMCIT) IMQ2016-53 IE2016-168 MVE2016-76
(To be available after the conference date) [more] IMQ2016-53 IE2016-168 MVE2016-76
pp.193-196
VLD 2017-03-02
09:50
Okinawa Okinawa Seinen Kaikan Reliability enhancement of Hierarchical data reading circuit of Wafer scale mask ROM
Takaaki Yokoyama, Ochi Hiroyuki (Ritsumeikan Univ) VLD2016-110
In the national libraries of developed countries, there is a demand to store large amounts of data in a digital form ove... [more] VLD2016-110
pp.49-54
DC 2015-06-16
16:00
Tokyo Kikai-Shinko-Kaikan Bldg. Performance Evaluation of Dependability Improvement Methods for Multiple Core Systems based on Markov Models
Masashi Imai (Hirosaki Univ.), Tomohiro Yoneda (NII) DC2015-20
In embedded systems, multiple core system is a promising architecture not only for performance improvement, but also for... [more] DC2015-20
pp.25-30
DC, CPSY 2015-04-17
09:50
Tokyo   A Proposal of Time-Lag-Less n-Fault-Tolerant Control System
Hitoshi Iwai CPSY2015-3 DC2015-3
In a conventional multi-modular majority voting redundancy for real-time hazard control the first processing step is tha... [more] CPSY2015-3 DC2015-3
pp.13-18
DC 2014-12-19
14:40
Toyama   A Proposal of Fault-Mask Triple Modular Redundancy with Certification and Integrity-check Code
Hitoshi Iwai DC2014-71
It must prove that output data of a function module and that of another function module are the same to check an integri... [more] DC2014-71
pp.25-28
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-28
15:35
Oita B-ConPlaza Some Studies of n-Fault-Tolerant System with Voting Switches
Hitoshi Iwai VLD2014-111 DC2014-65
This paper proposes n-fault-tolerant system method of voting redundancy with multiplied function modules. In well-known ... [more] VLD2014-111 DC2014-65
pp.257-262
CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] 2012-03-03
14:30
Miyagi   Structure Search of Cascaded TMR for Pipelined Processors Based on Genetic Algorithm
Masayuki Arai, Hajime Ide, Kazuhiko Iwasaki (Tokyo Metro. Univ.) CPSY2011-94 DC2011-98
In this paper we discuss on the application of TMR (Triple Modular Redundancy) to every stage of pipelined processors, a... [more] CPSY2011-94 DC2011-98
pp.211-217
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2011-11-30
10:05
Miyazaki NewWelCity Miyazaki A DMR based Parmanent Error Locating Method for a Dependable FU Array
Yohei Hazama, Jun Yao, Takashi Nakada, Yasuhiko Nakashima (NAIST) CPSY2011-51
Triple Modular Redundancy (TMR) is widely used to locating the erroneous unit inside electronic device when the possibil... [more] CPSY2011-51
pp.47-52
RECONF 2011-05-12
13:30
Hokkaido Hokkaido Univ. (Faculty of Eng., B3 Bldg.) Context Synchronization Method for Reliable Softcore Processor System
Makoto Fujino, Noritaka Kai, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2011-5
SRAM-based FPGAs are vulnerable to a SEU,
which is induced by radiation effect.
The SEU's effects on configuration mem... [more]
RECONF2011-5
pp.25-30
ICD 2011-04-18
10:00
Hyogo Kobe University Takigawa Memorial Hall [Invited Talk] Trends and Multi-level-cell Technology of Spin Transfer Torque Memory
Takashi Ishigaki, Takayuki Kawahara, Riichiro Takemura, Kazuo Ono, Kenchi Ito (Hitachi), Hideo Ohno (Tohoku U.) ICD2011-1
A MLC (Multi-level cell) SPRAM (Spin transfer torque RAM) with series-stacked MTJs (Magnetic tunnel junctions) was devel... [more] ICD2011-1
pp.1-5
PRMU 2011-03-11
11:10
Ibaraki   Study of Extracting Moving Objects from Dynamic Stereo Images and Segmenting the Moving and Still Objects' Reconstructed 3D Shape -- Proposing a Method that Combines Temporal Modified-RANSAC and Graph-cut Utilizing Color, Structure and A-priori Probabilities --
Naotomo Tatematsu, Jun Ohya (Waseda Univ.) PRMU2010-280
This paper proposes a method that combines Temporal modified RANSAC and Graph-cut utilizing color, structure and A-prior... [more] PRMU2010-280
pp.253-258
ITE-MMS, MRIS, ITE-CE [detail] 2011-01-20
14:45
Osaka Shoshin-Kaikan Bldg. Toward an increase of the output power from MgO-based tunnel magnetoresistance devices
Yasutomo Masugata, Shota Ishibashi, Hiroyuki Tomita (Osaka Univ), Takeshi Seki, Hiroki Maehara (AIST), Takayuki Nozaki (Osaka Univ), Hitoshi Kubota, Akio Fukushima, Shinji Yuasa (AIST), Yoshishige Suzuki (Osaka Univ) MR2010-55
A steady magnetization precession induced by spin-torque was studied in magnetic tunnel junctions with an Fe-rich CoFeB ... [more] MR2010-55
pp.17-19
SDM 2010-11-11
13:00
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Trends of Magnetic Memory; Multi-Level-Cell Spin Transfer Torque Memory
Takashi Ishigaki, Takayuki Kawahara, Riichiro Takemura, Kazuo Ono, Kenchi Ito (Hitachi), Hideo Ohno (Tohoku U.) SDM2010-173
A MLC (Multi-level cell) SPRAM (Spin transfer torque RAM) with series-stacked MTJs (Magneto tunnel junctions) was develo... [more] SDM2010-173
pp.11-15
ED, SDM 2010-07-02
11:35
Tokyo Tokyo Inst. of Tech. Ookayama Campus The Impact of Current Controlled-MOS Current Mode Logic /Magnetic Tunnel Junction Hybrid Circuit for Stable and High-speed Operation
Tetsuo Endoh, Masashi Kamiyanagi, Masakazu Muraguchi, Takuya Imamoto, Takeshi Sasaki (Tohoku Univ.) ED2010-109 SDM2010-110
In order to realize Integrated Circuits (IC) with operation over the 10GHz range, conventional CMOS logic face critical ... [more] ED2010-109 SDM2010-110
pp.257-262
MRIS, ITE-MMS 2010-06-10
14:00
Miyagi RIEC Tohoku Univ. MR ratio and RA design of CPP-MR film for over 2Tb/in2 read sensors
Masayuki Takagishi, Kenichiro Yamada, Hitoshi Iwasaki, Hiromi Nu Fuke, Susumu Hashimoto (Toshiba Corp) MR2010-2
We estimated the current perpendicular to plane (CPP)-MR performance target required for HDD with areal density from 2Tb... [more] MR2010-2
pp.13-19
VLD, IPSJ-SLDM 2010-05-19
17:00
Fukuoka Kitakyushu International Conference Center Error Propagation Probability-based Selective TMR for Reliable Coarse-Grained Reconfigurable Architecture
Hiroshi Yuasa, Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato (Kyoto Univ.) VLD2010-4
Advancing CMOS process technology implies decreasing operating voltages, leaving LSI increasingly vulnerable to temporar... [more] VLD2010-4
pp.37-42
 Results 1 - 20 of 34  /  [Next]  
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