Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
SDM |
2024-01-31 12:35 |
Tokyo |
KIT Toranomon Graduate School (Primary: On-site, Secondary: Online) |
[Invited Talk]
Milli-Kelvin Analysis Revealing the Role of Band-edge States in Cryogenic MOSFETs Hiroshi Oka, Hidehiro Asai, Takumi Inaba, Shunsuke Shitakata, Hitoshi Yui, Hiroshi Fuketa, Shota Iizuka, Kimihiko Kato, Takashi Nakayama, Takahiro Mori (AIST) SDM2023-74 |
Toward large-scale quantum computers, cryogenic CMOS circuits have been developed to control and readout the qubits insi... [more] |
SDM2023-74 pp.1-4 |
NLP, CAS |
2023-10-06 15:10 |
Gifu |
Work plaza Gifu |
A PWM/digital Converter for Improved Conversion Resolution using Frequency Multiplicator Zhang He, Andrino Robles Roberto, Tomochika Harada (Yamagata Univ.) CAS2023-43 NLP2023-42 |
For IoT (Internet of Things) devices, a reduction in power consumption is desired. To reduce power consumption, researc... [more] |
CAS2023-43 NLP2023-42 pp.58-61 |
ICD, SDM, ITE-IST [detail] |
2022-08-08 14:15 |
Online |
|
Evaluation of Steep Subthreshold Slope Device "Dual-gate type PN-body Tied SOI-FET" for Ultra-low Voltage Operation Haruki Yonezaki, Jiro Ida, Takayuki Mori (KIT), Koichiro Ishibashi (UEC) SDM2022-38 ICD2022-6 |
In this study, we report the first prototype results of a Steep SS "Dual-Gate (DG) PN-Body Tied (PNBT) SOI-FET" for extr... [more] |
SDM2022-38 ICD2022-6 pp.17-20 |
SDM |
2019-01-29 09:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
[Invited Talk]
Multidomain Dynamics of Ferroelectric Polarization in Negative Capacitance State and its Impacts on Performances of Field-Effect Transistors Hiroyuki Ota, Tsutomu Ikegami, Koichi Fukuda, Junichi HattoriI, Hidehiro Asai, Kazuhiko Endo, Shinji Migita (AIST), Akira Toriumi (The Univ. of Tokyo) SDM2018-81 |
In this paper, we clarified the multidomain dynamics of ferroelectric polarization in the Negative Capacitance Field-Eff... [more] |
SDM2018-81 pp.1-4 |
SDM |
2018-11-09 15:55 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
[Invited Talk]
Characteristics and Ultralow Voltage Rectification Experiment on MOS Diode connection using Super Steep SS PN-Body Tied SOI-FET Shun Momose, Jiro Ida, Takuya Yamada, Takayuki Mori, Kenji Itoh (KIT), Koichiro Ishibashi (UEC), Yasuo Arai (KEK) SDM2018-76 |
In order to utilize the Radio Frequency (RF) signal power existing in the living environment, a RF rectifier that realiz... [more] |
SDM2018-76 pp.59-64 |
SDM |
2017-01-30 11:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
[Invited Talk]
Fully Coupled 3-D Device Simulation of Negative Capacitance FinFETs for Sub 10 nm Integration Hiroyuki Ota, Tsutomu Ikegami, Junichi Hattori, Koichi Fukuda, Shinji Migita (AIST), Akira Toriumi (The Univ. of Tokyo) SDM2016-133 |
Subthreshold operation of negative capacitance FinFETs (NC-FinFETs) at sub 10 nm gate length are analyzed with a newly d... [more] |
SDM2016-133 pp.13-16 |
SDM |
2016-06-29 10:40 |
Tokyo |
Campus Innovation Center Tokyo |
[Invited Lecture]
Design of SOI-FETs for Steep Slope Switching using Negative Capacitance in Ferroelectric Gate Insulators Hiroyuki Ota, Shinji Migita, Junichi Hattori, Koichi Fukuda (AIST), Akira Toriumi (The Univ. of Tokyo) SDM2016-34 |
This paper discusses a design of fully depleted silicon-on-insulator field-effect transistors with ferroelectric gate in... [more] |
SDM2016-34 pp.9-13 |
ICD, SDM |
2014-08-05 09:00 |
Hokkaido |
Hokkaido Univ., Multimedia Education Bldg. |
[Invited Talk]
Ultra-Low Voltage (0.1V) Operation of Threshold Voltage Self-Adjusting MOSFET and SRAM Cell Toshiro Hiramoto, Akitsugu Ueda, Seung-Min Jung, Tomoko Mizutani, Takuya Saraya (Univ. of Tokyo) SDM2014-71 ICD2014-40 |
A new Vth self-adjusting MOSFET operating at 0.1V is proposed, where Vth automatically decreases at on-state and increas... [more] |
SDM2014-71 ICD2014-40 pp.51-54 |
ICD |
2014-01-28 15:00 |
Kyoto |
Kyoto Univ. Tokeidai Kinenkan |
[Poster Presentation]
A Design of 0.5V Subthreshold Digital Phase Locked Loop using Simple Synchronization Unit. Kousuke Watanabe, Tomochika Harada (Yamagata Univ.) ICD2013-129 |
In this paper, we design and evaluate the 0.5V subthreshold DPLL circuit. Under synchronization, fine tuning operation i... [more] |
ICD2013-129 pp.67-72 |
ICD, ITE-IST |
2013-07-05 17:40 |
Hokkaido |
San Refre Hakodate |
Failure mode analysis for flip-flops at low voltages Takafumi Fujita, Junya Kawashima, Masayuki Hiromoto (Kyouto Univ.), Hiroshi Tsutsui (Hokkaido Univ.), Hiroyuki Ochi (Ritsumeikan Univ.), Takashi Sato (Kyouto Univ.) ICD2013-45 |
Towards the reducing power consumption, subthreshold circuit which operates at a low voltage below the threshold voltage... [more] |
ICD2013-45 pp.129-134 |
SDM, ED (Workshop) |
2012-06-27 13:15 |
Okinawa |
Okinawa Seinen-kaikan |
Investigation and Optimization of the n-channel and p-channel L-shaped Tunneling Field-Effect Transistors Sang Wan Kim (Seoul National Univ.), Woo Young Choi (Sogang Univ.), Min-Chul Sun, Hyun Woo Kim, Byung-Gook Park (Seoul National Univ.) |
Tunneling field-effect transistors (TFETs) have been regarded as next-generation ultra-low power devices thanks to low o... [more] |
|
ICD, ITE-IST |
2011-07-21 09:55 |
Hiroshima |
Hiroshima Institute of Technology |
A Sense Amplifier with High Speed Pre-Charge Operation for Ultra-Low-Voltage SRAM Chotaro Masuda, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa (Kove Univ.) ICD2011-22 |
We propose a current latch sense amplifier with
a current-reuse technique (CLSA-w/CR). The CLSA-w/CR is
capable of hig... [more] |
ICD2011-22 pp.7-12 |
ICD |
2010-12-16 15:10 |
Tokyo |
RCAST, Univ. of Tokyo |
[Poster Presentation]
A 0.5V Subthreshold CMOS Analog Amplifier with Sub-MHz Bandwidth Takashi Mori, Tomochika Harada, Koichi Matsushita, Sumio Okuyama (Yamagata Univ.) ICD2010-103 |
In this paper, we present an ultra-low voltage analog amplifier based on a folded cascode opamp using subthreshold opera... [more] |
ICD2010-103 pp.49-53 |
ICD (Workshop) |
2010-08-16 - 2010-08-18 |
Overseas |
Ho Chi Minh City University of Technology |
An Offset Compensation Method Using Subthreshold CMOS Operational Amplifiers for Fully Differential Amplifiers Tomoki Iida, Tetsuya Asai, Yoshihito Amemiya, Eiichi Sano (Hokkaido Univ.) |
An offset compensation method for fully differential amplifiers is described. The method uses a feedback bias circuit co... [more] |
|
ICD, ITE-IST |
2010-07-23 09:15 |
Osaka |
Josho Gakuen Osaka Center |
Implementation and Evaluation of a CMOS Subthreshold Analog Amplifier using 0.5V Power Supply Tomochika Harada (Yamagata Univ.) ICD2010-30 |
[more] |
ICD2010-30 pp.55-60 |
ICD, ITE-IST |
2009-10-02 17:50 |
Tokyo |
CIC Tokyo (Tamachi) |
Delay Variation Tolerant Subthreshold Digital Circuits for Ultra-Low Power Yuji Osaki, Tetsuya Hirose, Kei Matsumoto, Nobutaka Kuroki, Masahiro Numa (Kobe Univ.) ICD2009-62 |
Subthreshold LSIs can achieve ultra-low power. However, threshold voltage variations with temperature and fabrication pr... [more] |
ICD2009-62 pp.165-170 |
VLD, ICD |
2008-03-06 16:35 |
Okinawa |
TiRuRu |
Comparison of Power consumption between dynamic voltage scheme and multi-supply voltage scheme for system LSI Satoshi Hanami, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-155 ICD2007-178 |
Reduction of power dissipation caused by dynamic current, gate leakage current, and subthreshold leakage current of mult... [more] |
VLD2007-155 ICD2007-178 pp.67-72 |
ICD, ITE-IST |
2007-07-26 08:55 |
Hyogo |
|
CMOS voltage reference based on threshold voltage of a MOSFET Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya (Hokkaido Univ.) ICD2007-38 |
We developed a voltage reference circuit using MOSFETs operated in the subthreshold region, except for the MOS resistor ... [more] |
ICD2007-38 pp.5-10 |
ICD, SDM |
2006-08-17 11:45 |
Hokkaido |
Hokkaido University |
Critical temperature switch circuit with CMOS subthreshold region Atsushi Hagiwara, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya (Hokkaido Univ.) |
We propose a thermosensing circuit that changes its internal state abruptly at a threshold temperature. The circuit swit... [more] |
SDM2006-131 ICD2006-85 pp.37-42 |