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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM | 2024-01-31 12:35 |
Tokyo | KIT Toranomon Graduate School (Primary: On-site, Secondary: Online) |
[Invited Talk]
Milli-Kelvin Analysis Revealing the Role of Band-edge States in Cryogenic MOSFETs Hiroshi Oka, Hidehiro Asai, Takumi Inaba, Shunsuke Shitakata, Hitoshi Yui, Hiroshi Fuketa, Shota Iizuka, Kimihiko Kato, Takashi Nakayama, Takahiro Mori (AIST)  SDM2023-74 |
Toward large-scale quantum computers, cryogenic CMOS circuits have been developed to control and readout the qubits insi... [more] | SDM2023-74 pp.1-4 |
| NLP, CAS | 2023-10-06 14:50 |
Gifu | Work plaza Gifu | A Design and Evaluation of the Up/Down Counter Type PWM Adder Using the Subthreshold Region Gaku Abe, Andrino Robles Roberto, Takumi Nihei, Tomochika Harada (Yamagata Univ.) CAS2023-42 NLP2023-41 |
This paper presents the design and evaluation of a PWM adder circuit using up/down counters operating in the subthreshol... [more] | CAS2023-42 NLP2023-41 pp.53-57 |
| NLP, CAS | 2023-10-06 15:10 |
Gifu | Work plaza Gifu | A PWM/digital Converter for Improved Conversion Resolution using Frequency Multiplicator Zhang He, Andrino Robles Roberto, Tomochika Harada (Yamagata Univ.) CAS2023-43 NLP2023-42 |
For IoT (Internet of Things) devices, a reduction in power consumption is desired. To reduce power consumption, researc... [more] | CAS2023-43 NLP2023-42 pp.58-61 |
| SDM, ICD, ITE-IST [detail] | 2023-08-01 16:35 |
Hokkaido | Hokkaido Univ. Multimedia Education Bldg. 3F (Primary: On-site, Secondary: Online) |
Analysis of back bias effects and history phenomena in cryo 200nm SOIMOSFETs Ryusei Ri, Takayuki Mori (KIT), Hiroshi Oka, Takahiro Mori (AIST), Jiro Ida (KIT) SDM2023-42 ICD2023-21 |
In this paper, we report the results of our ongoing analysis of a peculiar phenomenon in 200 nm SOI MOSFETs, which occur... [more] | SDM2023-42 ICD2023-21 pp.32-35 |
| CCS | 2023-03-26 10:55 |
Hokkaido | RUSUTSU RESORT | A Stochastic Memory for Ultralow-Power IoT Devices and its Subthreshold CMOS Circuit Implementation Seiya Muramatsu, Kohei Nishida, Kota Ando (Hokkaido Univ.), Megumi Akai-Kasaya (Osaka Univ./Hokkaido Univ.), Tetsuya Asai (Hokkaido Univ.) CCS2022-68 |
We propose a CMOS circuit implementation of a memory circuit for ultralow-power IoT devices based on stochastic computin... [more] | CCS2022-68 pp.31-35 |
| SDM | 2022-11-11 11:30 |
Online | Online | Modeling of Super Steep Subthreshold Slope "PN Body Tied SOI-FET" by using Neural Network Nakata Kengo, Mori Takayuki, Ida Jiro (Kanazawa Inst. of Tech.) SDM2022-73 |
In this study, we examined how PN-Body Tied (PNBT) Silicon On Insulator (SOI)-FETs, a novel device structure with steep ... [more] | SDM2022-73 pp.44-48 |
| ICD, SDM, ITE-IST [detail] | 2022-08-08 14:15 |
Online | Evaluation of Steep Subthreshold Slope Device "Dual-gate type PN-body Tied SOI-FET" for Ultra-low Voltage Operation Haruki Yonezaki, Jiro Ida, Takayuki Mori (KIT), Koichiro Ishibashi (UEC) SDM2022-38 ICD2022-6 |
In this study, we report the first prototype results of a Steep SS "Dual-Gate (DG) PN-Body Tied (PNBT) SOI-FET" for extr... [more] | SDM2022-38 ICD2022-6 pp.17-20 |
|
| ICD, SDM, ITE-IST [detail] | 2020-08-07 11:00 |
Online | Online | CMOS Inverter Transfer Characteristics on Steep SS “PN-Body Tied SOI-FET” Shota Ishiguro, Jiro Ida, Takayuki Mori (KIT), Koichiro Ishibashi (UEC) SDM2020-8 ICD2020-8 |
In this study, we report the CMOS Inverter Transfer Characteristics on Steep SS “PN-Body Tied SOI-FET” proposed in our l... [more] | SDM2020-8 ICD2020-8 pp.37-40 |
| MW (2nd) |
2020-05-13 - 2020-05-15 |
Overseas | CU, Bangkok, Thailand (Postponed) |
RF Measurement of Steep Subthreshold Slope "PN-Body Tied SOI FET" Mitsuhiro Yuizono, Jiro Ida, Takayuki Mori (Kanazawa Inst of Tech) |
RF measured data of super steep subthreshold slope "PN-Body Tied (PNBT) SOI-FET" was obtained for the first time. The te... [more] | |
| SDM, ICD, ITE-IST [detail] | 2019-08-09 14:10 |
Hokkaido | Hokkaido Univ., Graduate School /Faculty of Information Science and | Effect of Vsub and Positive Charge in Buried Oxide on Super Steep SS “PN Body-Tied SOI-FET” Wataru Yabuki, Jiro Ida, Takayuki Mori (KIT), Koichiro Ishibashi (UEC), Yasuo Arai (KEK) SDM2019-51 ICD2019-16 |
In this study, We report the effect of the substrate bias (Vsub) and the positive charge (Qox) in the buried oxide (BOX)... [more] | SDM2019-51 ICD2019-16 pp.89-93 |
| SDM | 2019-01-29 09:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Multidomain Dynamics of Ferroelectric Polarization in Negative Capacitance State and its Impacts on Performances of Field-Effect Transistors Hiroyuki Ota, Tsutomu Ikegami, Koichi Fukuda, Junichi HattoriI, Hidehiro Asai, Kazuhiko Endo, Shinji Migita (AIST), Akira Toriumi (The Univ. of Tokyo) SDM2018-81 |
In this paper, we clarified the multidomain dynamics of ferroelectric polarization in the Negative Capacitance Field-Eff... [more] | SDM2018-81 pp.1-4 |
| SDM | 2019-01-29 09:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Assessment of Steep-Subthreshold Swing Behaviors in Ferroelectric Field-Effect Transistors Shinji Migita, Hiroyuki Ota (AIST), Akira Thorium (U. Tokyo) SDM2018-82 |
Steep-subthreshold swing (steep-SS) behaviors are observable in recent ferroelectric-gate field-effect transistors (FE-F... [more] | SDM2018-82 pp.5-8 |
| RCS, AP (Joint) |
2018-11-20 10:25 |
Okinawa | Okinawa Industry Support Center | Interference-Aided Detection of Subthreshold Signal Using Stochastic Resonance Receiver
-- Characteristic Evaluation Using PSK Modulation Method -- Shintaro Hiraokka, Takaya Yamazato (Nagoya Univ.), Shintaro Arai (Okayama Univ. of Scienc), Yukihiro Tadokoro, Hiroya Tanaka (Toyota Central R&D Labs., Inc) RCS2018-179 |
Stochastic resonance is a nonlinear phenomenon in which the performance of the system is improved by adding noise of app... [more] | RCS2018-179 pp.7-12 |
| SDM | 2018-11-09 15:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Characteristics and Ultralow Voltage Rectification Experiment on MOS Diode connection using Super Steep SS PN-Body Tied SOI-FET Shun Momose, Jiro Ida, Takuya Yamada, Takayuki Mori, Kenji Itoh (KIT), Koichiro Ishibashi (UEC), Yasuo Arai (KEK) SDM2018-76 |
In order to utilize the Radio Frequency (RF) signal power existing in the living environment, a RF rectifier that realiz... [more] | SDM2018-76 pp.59-64 |
| SDM, ICD, ITE-IST [detail] | 2018-08-07 14:25 |
Hokkaido | Hokkaido Univ., Graduate School of IST M Bldg., M151 | Experiment of Ultralow Voltage Rectification by Super Steep SS "PN-Body Tied SOI-FET" Shun Momose, Jiro Ida, Takuya Yamada, Takayuki Mori, Kenji Itoh (KIT), Koichiro Ishibashi (UEC), Yasuo Arai (KEK) SDM2018-31 ICD2018-18 |
In order to construct a rectifier that function with µW power, it is necessary to develop a new diode technology. The co... [more] | SDM2018-31 ICD2018-18 pp.31-34 |
| SDM, ICD, ITE-IST [detail] | 2018-08-07 15:00 |
Hokkaido | Hokkaido Univ., Graduate School of IST M Bldg., M151 | A 0.6V 9bit PWM Differential Arithmetic Circuit Fumiya Kojima, Tomochika Harada (Yamagata Univ) SDM2018-32 ICD2018-19 |
In this paper, we design and evaluate the analog / PWM conversion circuit and the PWM differential arithmetic circuit wh... [more] | SDM2018-32 ICD2018-19 pp.35-40 |
| SDM, ICD, ITE-IST [detail] | 2018-08-08 09:45 |
Hokkaido | Hokkaido Univ., Graduate School of IST M Bldg., M151 | Understanding Temperature Effect on Subthreshold Slope Variability in Bulk and SOTB MOSFETs Shuang Gao, Tomoko Mizutani, Kiyoshi Takeuchi, Masaharu Kobayashi, Toshiro Hiramoto (Univ. Tokyo) SDM2018-37 ICD2018-24 |
We present a new finding that subthreshold slope (SS) variability is reduced at high temperature in both bulk and silico... [more] | SDM2018-37 ICD2018-24 pp.65-70 |
| VLD, HWS (Joint) |
2018-03-02 09:00 |
Okinawa | Okinawa Seinen Kaikan | On-chip and ultra low current measurement circuit based on potentiostat method Daishi Isogai, Takaaki Shirakawa, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2017-119 |
We propose a current measurement circuit using on - chip high resistance by MOSFET. Due to advances in biosensing techno... [more] | VLD2017-119 pp.181-186 |
| SDM, ICD, ITE-IST [detail] | 2017-08-02 11:35 |
Hokkaido | Hokkaido-Univ. Multimedia Education Bldg. | Gate Controlled Diode Characteristics of Super Steep Subthreshold slope PN-Body Tied SOI-FET for high Efficiency RF Energy Harvesting Shun Momose, Jiro Ida, Takayuki Mori, Takahiro Yoshida, Junpei Iwata, Takashi Horii, Takahiro Furuta, Takuya Yamada, Daichi Takamatsu, Kenji Itoh (KIT), Koichiro Ishibashi (UEC), Yasuo Arai (KEK) SDM2017-45 ICD2017-33 |
The gate controlled diode characteristics with our newly super steep subthreshold slope (SS) “PN-Bode Tied SOI FET” was ... [more] | SDM2017-45 ICD2017-33 pp.109-114 |
| SDM | 2017-01-30 11:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Fully Coupled 3-D Device Simulation of Negative Capacitance FinFETs for Sub 10 nm Integration Hiroyuki Ota, Tsutomu Ikegami, Junichi Hattori, Koichi Fukuda, Shinji Migita (AIST), Akira Toriumi (The Univ. of Tokyo) SDM2016-133 |
Subthreshold operation of negative capacitance FinFETs (NC-FinFETs) at sub 10 nm gate length are analyzed with a newly d... [more] | SDM2016-133 pp.13-16 |
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