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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 20  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM 2021-01-28
14:05
Online Online [Invited Talk] Secure 3D CMOS Chip Stacks with Backside Buried Metal Power Delivery Networks for Distributed Decoupling Capacitance
Kazuki Monta (Kobe Univ.) SDM2020-51
In semiconductor integrated circuits, power signal integrity(PSI) and electromagnetic compatibility caused by power supp... [more] SDM2020-51
pp.8-12
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-07
14:55
Kumamoto Kumamoto-Kenminkouryukan Parea Simulation Techniques for EMC Compliant Design of Automotive IC Chips and Modules
Akihiro Tsukioka, Makoto Nagata, Kohki Taniguchi, Daisuke Fujimoto (Kobe Univ.), Rieko Akimoto, Takao Egami, Kenji Niinomi, Takeshi Yuhara, Sachio Hayashi (TOSHIBA), Rob Mathews, Karthik Srinivasan, Ying-Shiun Li, Norman Chang (ANSYS) CPM2017-84 ICD2017-43 IE2017-69
In recent years, electromagnetic compatibility (EMC) becomes a major concern among IC chips. EMC is characterized in two... [more] CPM2017-84 ICD2017-43 IE2017-69
pp.27-32
EMCJ, IEE-EMC 2014-06-20
10:35
Hyogo Kobe Univ. Side-Channel Leakage on Silicon Substrate of CMOS Cryptographic Chip
Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata (Kobe Univ.), Yu-ichi Hayashi, Naofumi Homma (Tohoku Univ.), Shivam Bhasin, Jean-Luc Danger (Telecom Paristech) EMCJ2014-10
Power supply currents of CMOS digital circuits partly flow through a silicon substrate in their returning (ground) paths... [more] EMCJ2014-10
pp.1-6
EMCJ 2013-09-13
11:00
Hokkaido Hokkaido Univ. Transmission Quantity Investigation for Substrate Integrated Waveguides on Shield Enclosure Apertures
Yasuhiro Shiraki, Naoto Oka, Yuichi Sasaki, Hideyuki Oh-hashi, Satoshi Yoneda (Mitsubishi Electric) EMCJ2013-50
We investigated a substrate integrated waveguide (SIW) resonators in order to suppress electromagnetic noise from apert... [more] EMCJ2013-50
pp.7-11
EMCJ 2013-07-11
12:45
Tokyo Kikai-Shinko-Kaikan Bldg. Impedance Balance Control for Suppression of Substrate Noise Coupling in CMOS IC
Masaaki Maeda, Tohlu Matsushima, Takashi Hisakado, Osami Wada (Kyoto Univ) EMCJ2013-30
Simultaneous switching current generated by operation of a CMOS circuit is injected into the CMOS substrate, and causes ... [more] EMCJ2013-30
pp.15-20
EMCJ 2012-01-27
11:30
Fukuoka Kyushu Univ. Rogowski Probe using laminated Substrates for High Frequency
Yoichiro Suzuki, Syuichi Kono (SOKEN), Tomonori Kimura, Ryohei Kataoka (DENSO) EMCJ2011-118
High accuracy measurement technology of high frequency ringing current g
enerated by switching of power device is requi... [more]
EMCJ2011-118
pp.41-45
ICD, ITE-IST 2011-07-22
10:25
Hiroshima Hiroshima Institute of Technology Analysis Methods of Substrate Sensitivity in an Analog Circiut
Satoshi Takaya, Yoji Bando (Kobe Univ.), Toru Ohkawa, Masaaki Souda, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami (MIRAI-Selete), Makoto Nagata (Kobe Univ.) ICD2011-28
Substrate noise sensitivity of an analog circuit consists of the sensitivity of a device and noise propagation from the ... [more] ICD2011-28
pp.73-78
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2010-11-29
11:20
Fukuoka Kyushu University A Consideration of Substrate Noise Sensitivity of Analog Elements
Satoshi Takaya, Yoji Bando, Takashi Hasegawa (Kobe Univ.), Toru Ohkawa, Masaaki Souda, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami (MIRAI-Selete), Makoto Nagata (Kobe Univ.) CPM2010-126 ICD2010-85
Measure substrate sensitivity of differential amplifiers in a 90 nm CMOS technology with more than 32 different geometor... [more] CPM2010-126 ICD2010-85
pp.13-17
ICD 2009-12-14
13:30
Shizuoka Shizuoka University (Hamamatsu) [Poster Presentation] Simulation of Substrate Noise Impact on CMOS Analog Circuit
Satoshi Takaya, Yoji Bando, Makoto Nagata (Kobe Univ.) ICD2009-81
We have measured and simulated substrate noise impact on basic analog amplifier using 90-nm CMOS test chip. To measure s... [more] ICD2009-81
pp.31-34
ICD 2009-12-14
13:30
Shizuoka Shizuoka University (Hamamatsu) [Poster Presentation] Measurement and Simulation of Substrate Coupling of CMOS-RF Circuit
Naoya Azuma, Makoto Nagata (Kobe Univ.) ICD2009-83
Susceptibility of radio frequency (RF) circuits against environmental noises was evaluated by way of direct power inject... [more] ICD2009-83
pp.39-42
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2009-12-02
11:20
Kochi Kochi City Culture-Plaza A Reference CMOS Circuit Structure for Evaluation of Power Supply Noise
Tetsuro Matsuno, Daisuke Kosaka (Kobe Univ.), Makoto Nagata (Kobe Univ./ CREST-JST) CPM2009-137 ICD2009-66
Accurate understandings of dynamic noises in power delivery networks of very large scale integration (VLSI) chips are st... [more] CPM2009-137 ICD2009-66
pp.19-22
ICD, ITE-IST 2009-10-01
10:00
Tokyo CIC Tokyo (Tamachi) Evaluation and Analysis of Substrate Noise in Microprocessor
Yoji Bando (Kobe Univ.), Daisuke Kosaka (A-R-Tec), Goichi Yokomizo, Kunihiko Tsuboi (STARC), Ying Shiun Li, Shen Lin (Apache), Makoto Nagata (Kobe Univ./A-R-Tec) ICD2009-35
An integrated power and substrate noise analysis environment targeting systems-on-chip (SoC) design was verified through... [more] ICD2009-35
pp.11-14
EMCJ 2009-06-05
13:35
Tokyo Tokyo Big Sight (Tokyo International Exihibition Center) A Study on Shield Structure of a Connector Substrate with Single Point Ground Plane Connection
Satoshi Yoneda (Mitsubishi Electric Corp.), Takefumi Kumamoto (Mitsubishi Electric Engineering Co.Ltd.), Chiharu Miyazaki, Naoto Oka (Mitsubishi Electric Corp.) EMCJ2009-28
In recent years, noise radiation from a connector substrate which consists of printed boards and a connector sometimes c... [more] EMCJ2009-28
pp.35-39
EMCJ 2009-04-24
16:40
Okayama   [Special Talk] *
Atsushi Iwata (Hiroshima Univ./A-R-Tec Corp.,) EMCJ2009-8
Based on accurate noise measurement techniques and simulation models for supply/substrate noise, effects of crosstalk no... [more] EMCJ2009-8
pp.39-44
ICD, SDM 2008-07-17
09:00
Tokyo Kikai-Shinko-Kaikan Bldg. Impact of the Different Nature of Interface Defect States on the NBTI and 1/f noise of High-k / Metal Gate pMOSFETs between (100) and (110) Crystal Orientations
Motoyuki Sato, Yoshihiro Sugita, Takayuki Aoyama, Yasuo Nara, Yuzuru Ohji (Selete) SDM2008-128 ICD2008-38
Using (110) substarate is one of promissing candidate for pMOSTET boost technology. (110) surface shows not only higher ... [more] SDM2008-128 ICD2008-38
pp.1-6
VLD, IPSJ-SLDM 2008-05-09
10:00
Hyogo Kobe Univ. [Invited Talk] NoizeProblems in LSI Design:Challenges and Approaches
Makoto Nagata (Kobe Univ.)
Digital designs intending high-speed and low-power consumption necessarily deal with dynamic power supply noise, for suc... [more] VLD2008-7
pp.1-6
CPM, ICD 2008-01-17
10:05
Tokyo Kikai-Shinko-Kaikan Bldg ptimization of Active Substrate Noise Cancellng Technique Using Multi di/dt Detectors
Toru Nakura, Taisuke Kazama, Makoto Ikeda, Kunihiro Asada (The Univ. of Tokyo) CPM2007-130 ICD2007-141
This paper demonstrates study on a feedforward active substrate noise cancelling technique using a power supply di/dt de... [more] CPM2007-130 ICD2007-141
pp.11-16
ICD, VLD 2007-03-08
17:10
Okinawa Mielparque Okinawa [Invited Talk] Measurements and reduction of power line noises in SoCs
Makoto Ikeda, Kunihiro Asada (Tokyo Univ.)
This paper describes power bounce measurement technique in SoCs and active substrate noise reduction techniques. Noise m... [more] VLD2006-139 ICD2006-230
pp.121-126
ICD, ITE-IST 2006-07-27
10:00
Shizuoka   Evaluation of Digital Crosstalk Noise to fully DIfferential VCO
Akihiro Toya (Hiroshima Univ.), Yoshitaka Murasaka, Takafumi Ohmoto (A-R-Tec Corp.), Atsushi Iwata (Hiroshima Univ.)
In accordance with the rapid increase of operation frequencies of CMOS circuits, radio-frequency system-on-a-chip (RF-SO... [more] ICD2006-60
pp.1-6
ICD, SDM 2005-08-18
13:25
Hokkaido HAKODATE KOKUSAI HOTEL Isolation Strategy against Substrate Coupling in CMOS Mixed-Signal/RF Circuits
Daisuke Kosaka, Makoto Nagata (Kobe Univ.), Yoshitaka Murasaka, Atsushi Iwata (A-R-Tec Corp.)
A deep n-well guard-ring, DNW-GR, provides effective isolation from substrate-coupled high frequency noises in combinati... [more] SDM2005-136 ICD2005-75
pp.49-54
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