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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 7件中 1~7件目  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS, VLD 2019-02-28
10:25
Okinawa Okinawa Ken Seinen Kaikan Evaluation of low power consumption Standard Cell Memory (SCM) using body-bias control in Silicon-on-Thin-BOX MOSFET:SOTB
Ryo Magasaki, Yusuke Yoshida (Shibaura Inst. of Tech.), Hideharu Amano (Keio Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2018-108 HWS2018-71
In recent years, IoT devices are rapidly increasing. One of the IoT devices is a sensor node and a small medical device... [more] VLD2018-108 HWS2018-71
pp.91-96
VLD, HWS
(Joint)
2018-03-02
11:20
Okinawa Okinawa Seinen Kaikan Energy Reduction of Standard-Cell Memory Exploiting Selective Activation
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.) VLD2017-124
On-chip memories have a large impact on energy-efficiency of LSI circuits. This paper discusses energy-efficient on-chip... [more] VLD2017-124
pp.211-216
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-06
14:55
Kumamoto Kumamoto-Kenminkouryukan Parea Leakage Energy Reduction for Digital Embedded Memory using Dynamic Multi Body Bias Control
Yusuke Yoshida, Kimiyoshi Usami (SIT) VLD2017-33 DC2017-39
Embedded memory macros are major central building blocks of any microprocessor and greatly affect power dissipation. In ... [more] VLD2017-33 DC2017-39
pp.37-42
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-29
09:00
Osaka Ritsumeikan University, Osaka Ibaraki Campus Design and Implementation Methodology of Low-power Standard cell memory with optimized body-bias separation in Silicon-on-Thin-BOX (SOTB)
Yusuke Yoshida, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2016-53 DC2016-47
We focus on the Standard Cell Memory (SCM) as another option to supersede SRAM for low-voltage operation. This paper des... [more] VLD2016-53 DC2016-47
pp.55-60
VLD, CAS, MSS, SIP 2016-06-17
09:50
Aomori Hirosaki Shiritsu Kanko-kan Design and Evaluation of MTJ-based Standard Cell Memory
Junya Akaike, Masaru Kudo, Kimiyoshi Usami (SIT) CAS2016-19 VLD2016-25 SIP2016-53 MSS2016-19
With the spread of portable devices, products with high performance and long battery life are required. In this paper, w... [more] CAS2016-19 VLD2016-25 SIP2016-53 MSS2016-19
pp.103-108
VLD 2016-03-01
17:05
Okinawa Okinawa Seinen Kaikan Low-power Standard Cell Memory using Silicon-on-Thin-BOX (SOTB) and Body-bias Control
Yusuke Yoshida, Masaru Kudo, Kimiyoshi Usami (SIT) VLD2015-130
In recent years, energy harvesting and sensor node have attracted a lot of attention. Therefore, a memory which can redu... [more] VLD2015-130
pp.111-116
RECONF 2011-09-26
11:10
Aichi Nagoya Univ. Feasibility study of nonvolatile reconfiguralbe device by using a standard CMOS logic process
Shuji Kunimitsu, Mamoru Terauchi, Kazuya Tanigawa, Tetsuo Hironaka (HCU), Masayuki Sato, Takashi Ishiguro (TAIYO YUDEN) RECONF2011-23
In this paper, we consider the realization of nonvolatile PLD, based on the new recon gurable device
architecture MPLD.... [more]
RECONF2011-23
pp.7-12
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