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Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] 2022-01-24
14:50		 Online Online Implementation of a RISC-V SMT Core in Virtual Engine Architecture
Hidetaro Tanaka, Tomoaki Tanaka, Keita Nagaoka, Ryosuke Higashi (TUAT), Tsutomu Sekibe, Shuichi Takada (ArchiTek), Hironori Nakajo (TUAT) VLD2021-57 CPSY2021-26 RECONF2021-65		 The RISC-V core which supports simultaneous multithreading (SMT) on a heterogeneous virtual engine architecture has been... [more] VLD2021-57 CPSY2021-26 RECONF2021-65
pp.43-48
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2015-12-03
12:05		 Nagasaki Nagasaki Kinro Fukushi Kaikan A Low Latency Real-Time Execution on Dependable Responsive Multithreaded Processor II
Yusuke Hatori, Kohei Osawa (Keio Univ.), Keigo Mizotani (Nintendo), Hiroyuki Chishiro, Nobuyuki Yamasaki (Keio Univ.) CPSY2015-75		 Recent embedded real-time systems have required multiprocessors to achieve not only real-time con-
straints but also hi... [more]		 CPSY2015-75
pp.81-86
CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] 2015-03-06
14:50		 Kagoshima   A Resource Utilization Aware Method to Improve Throughput on RMT Processor
Taro Murata, Kensuke Kaneda, Masayoshi Takasu, Keigo Mizotani, Yusuke Hatori, Nobuyuki Yamasaki (Keio Univ.) CPSY2014-166 DC2014-92		 SMT (Simultaneous MultiThreading) architecture is suitable for embedded processors which have area
constraints, it is b... [more]		 CPSY2014-166 DC2014-92
pp.25-30
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
16:30		 Kanagawa Hiyoshi Campus, Keio University A Low Latency Real-Time Execution on Dependable Responsive Multithreaded Processor
Keigo Mizotani, Yusuke Hatori, Yusuke Kumura, Masayoshi Takasu, Hiroyuki Chishiro, Nobuyuki Yamasaki (Keio Univ.) VLD2014-149 CPSY2014-158 RECONF2014-82		 In recent embedded real-time systems, there are many systems with both hard real-time tasks and soft real-time tasks. Wh... [more] VLD2014-149 CPSY2014-158 RECONF2014-82
pp.227-232
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