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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2015-12-01
13:10		 Nagasaki Nagasaki Kinro Fukushi Kaikan Implementation of ECDSA Using Gate-level Pipelined Self-synchronous Circuit
Masato Tamura, Makoto Ikeda (Univ. of Tokyo) VLD2015-39 DC2015-35		 In this paper, we investigated the implementation method of elliptic curve digital signature algorithm using self-synchr... [more] VLD2015-39 DC2015-35
pp.7-12
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2014-11-28
10:05		 Oita B-ConPlaza Optimization for gate-level pipelined self-synchrnous circuit
Atsushi Ito, Makoto Ikeda (Univ. of Tokyo) VLD2014-107 DC2014-61		 With the down-scaling, circuit which has higher robustness is demanded. Dual-pipeline self synchronous circuit have inhe... [more] VLD2014-107 DC2014-61
pp.233-238
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