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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] |
2022-03-10 13:50 |
Online |
Online |
Implementation of an Application Mapping Tool for a Circuit-Switched Multi-FPGA System Kohei Ito (Keio Univ.), Ryota Yasudo (Kyoto Univ.), Hideharu Amano (Keio Univ.) CPSY2021-48 DC2021-82 |
(To be available after the conference date) [more] |
CPSY2021-48 DC2021-82 pp.20-25 |
VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-02 09:20 |
Online |
Online |
The Implementation of a Hybrid Router with Dynamic Communication Priority Changes on a Multi-FPGA System Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano (Keio Univ.) VLD2021-36 ICD2021-46 DC2021-42 RECONF2021-44 |
We are currently developing a multi-FPGA system, Flow-in-Cloud (FiC) system. FiC directly interconnects multiple middle-... [more] |
VLD2021-36 ICD2021-46 DC2021-42 RECONF2021-44 pp.111-116 |
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] |
2020-01-22 14:20 |
Kanagawa |
Raiosha, Hiyoshi Campus, Keio University |
Implementation and Evaluation of a Router on a Multi-FPGA System Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Yugo Yamauchi, Kazuei Hironaka, Hideharu Amano (Keio Univ.) VLD2019-59 CPSY2019-57 RECONF2019-49 |
The trade-off between power efficiency and performance is important in large-scale computing systems like a datacenter. ... [more] |
VLD2019-59 CPSY2019-57 RECONF2019-49 pp.31-36 |
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] |
2020-01-22 14:45 |
Kanagawa |
Raiosha, Hiyoshi Campus, Keio University |
Performance Evaluation of Using Multi-Switch on a Multi-FPGA System Kohei Ito, Kensuke Iizuka, Yugo Yamauchi, Kazuei Hironaka (Keio Univ.), Yao Hu, Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) VLD2019-60 CPSY2019-58 RECONF2019-50 |
Flow-in-Cloud(FiC) is a system which consists of multiple middle-range FPGAs connected by high-speed serial links, and i... [more] |
VLD2019-60 CPSY2019-58 RECONF2019-50 pp.37-42 |
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