IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 7 of 7  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
WPT
(2nd)
2019-10-31
- 2019-11-02
Overseas Xidian University High Efficiency Wireless Distribution Unit Based on ICPT
Ma Liang, Liu zhigang, Zhang Xiaofeng, Zhu liying (BISEE)
 [more]
OCS, LQE, OPE 2019-10-18
15:30
Kagoshima   Study on optical vortex splitter on Si substrate using optical topology
Sho Okada, Tomohiro Amemiya, Koichi Saito, Hibiki Kagami, Makoto Tanaka, Nobuhiko Nishiyama (Tokyo Tech), Xiao Hu (NIMS) OCS2019-49 OPE2019-87 LQE2019-65
We propose an optical vortex splitter that can be integrated into a conventional silicon photonics optical circuit. The ... [more] OCS2019-49 OPE2019-87 LQE2019-65
pp.113-118
EE, WPT, IEE-SPC 2018-07-03
13:40
Hokkaido Hokkaido University Proposal of Design Method Based on Power Factor Compensation for SS and SP Topology of Capacitive Power Transfer with Resonance Coupling
Kenta Suzuki, Takehiro Imura, Yoichi Hori (The Univ. of Tokyo) WPT2018-25
Capacitive power transfer has advantages such as lower cost and lighter weight for the equipment materials than IPT. How... [more] WPT2018-25
pp.97-100
AP, WPT
(Joint)
2017-01-19
11:10
Hiroshima Hiroshima Institute of Technology Basic Study on Circuit Topology for High Efficiency Wireless Power Transfer through Metal Wall
Mai Otsuka, Takehiro Imura, Hiroshi Fujimoto, Yoichi Hori (UTokyo) WPT2016-48
The aim of this research is feeding power wirelessly to the sensor surrounded by the metal wall. Various circuit configu... [more] WPT2016-48
pp.33-38
ICD, CPSY 2016-12-16
09:40
Tokyo Tokyo Institute of Technology Automatic Design of Bias Circuit Based on the Results of Characterized MOSFET
Kento Suzuki, Nobukazu Takai, Yoshiki Sugawara, Kazuto Okochi, Satoshi Yoshizawa, Tsukasa Ishii, Saki Shinoda, Masafumi Fukuda (Gunma Univ.) ICD2016-91 CPSY2016-97
It is difficult to design optimal analog circuit in a short time in terms of designing flexibility. In an analog circuit... [more] ICD2016-91 CPSY2016-97
pp.119-122
CAS, NLP 2007-10-19
15:20
Tokyo Musashi Institute of Technology An Electric Circuit Analogue of Adaptive Transport Networks in True Slime Mold
Yuta Kondo, Hisa-Aki Tanaka (Univ. of Electro-Comm.) CAS2007-63 NLP2007-91
We propose an electrical circuit analogue of adaptive transport networks in true slime mold.
From systematic simulation... [more]
CAS2007-63 NLP2007-91
pp.65-69
NLP 2004-07-16
13:25
Shizuoka Shizuoka Univ. Proposal of Modified Nonlinear Networks Reduction Technique and Its Estimation
Tsutomu Ishida, Takashi Mine, Hidemasa Kubota (Shizuoka Univ.), Takayuki Watanabe (Univ. of Shizuoka), Hideki Asai (Shizuoka Univ.)
In this report, we propose the nonlinear network reduction technique independent of the network topology. This technique... [more] NLP2004-28
pp.25-30
 Results 1 - 7 of 7  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan