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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 7 of 7  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
KBSE, SC 2019-11-08
11:30
Nagano Shinshu University A Method to Analyze NuSMV Counterexamples for Defect Cause Analysis
Yutaro Ohike, Shinpei Ogata (Shinshu Univ.), Yoshitaka Aoki (Nihon Unisys, Ltd.), Hiroyuki Nakagawa (Osaka Univ.), Kazuki Kobayashi, Kozo Okano (Shinshu Univ.) KBSE2019-24 SC2019-21
Many state variables that are defined in a model may appear as conditional expressions in one specification on model che... [more] KBSE2019-24 SC2019-21
pp.7-12
MBE 2016-06-17
13:25
Hokkaido Hokkaido University Verification of a management system for ventilator using model checking
Hisashi Miyazaki, Takayuki Torigoe, Isao Kayano (Kawasaki Univ of Medical Welfare), Yasuo Ogasawara (Kawasaki Medical School/Kawasaki Univ of Medical Welfare) MBE2016-14
In a hospital, medical staffs may be used a system which is developed by themselves for promotion of streamlining and im... [more] MBE2016-14
pp.27-30
VLD 2016-02-29
13:30
Okinawa Okinawa Seinen Kaikan Tool Support for Verifying Large Scale Hardware Design with Verilog-HDL
Yuta Morimitsu, Tomoyuki Yokogawa (Okayama Prefectural Univ.), Masafumi Kondo, Hisashi Miyazaki (Kawasaki Univ. of Medical Welfare), Yoichiro Sato, Kazutami Arimoto (Okayama Prefectural Univ.), Norihiro Yoshida (Nagoya Univ.) VLD2015-111
In this paper, we developed a tool supporting formal verification of large scale hardware design described by Verilog-HD... [more] VLD2015-111
pp.1-6
MSS 2015-03-06
13:55
Ishikawa IT Business Plaza Musashi The symbolic model checking by the model extraction from embedded assembly program
Tomonori Kato, Ryosuke Konoshita, Kohei Sakurai, Satoshi Yamane (Kanazawa Univ.) MSS2014-102
Embedded systems have been widely used. In addition, embedded systems have been gradually complicated.It is important to... [more] MSS2014-102
pp.65-70
KBSE, SS, IPSJ-SE [detail] 2014-07-11
13:10
Hokkaido Furano-Bunka-Kaikan On Coverage Criteria for State Transition Testing and Model Checker-Based Test Case Generation
Cassia de Souza Carvalho, Tatsuhiro Tsuchiya (Osaka Univ.) SS2014-23 KBSE2014-26
State Transition Testing is an important category of software testing.
Our work in progress focuses on a coverage crit... [more]
SS2014-23 KBSE2014-26
pp.149-154
VLD 2014-03-05
15:45
Okinawa Okinawa Seinen Kaikan A Case Study of Symbolic Model Checking for Verilog-HDL Hardware Design
Tomoyuki Yokogawa, Daichi Higashiyama (Okayama Pref. Univ.), Masafumi Kondo (Kawasaki Univ. of Medical Welfare), Yoichiro Sato, Kazutami Arimoto (Okayama Pref. Univ.) VLD2013-166
In this paper, we show a case study where a design of 8bit microcomputer M8R, which is described by Verilog-HDL, is veri... [more] VLD2013-166
pp.177-182
DC, CPSY, IPSJ-SLDM, IPSJ-EMB 2008-03-28
13:00
Kagoshima   Automatically Generating Testcases with the NuSMV Model Checker
Masaya Kadono, Tatsuhiro Tsuchiya, Tohru Kikuno (Osaka Univ.) DC2007-110 CPSY2007-106
There are various testing methods of improving the reliability of software.In this study, we consider state transition t... [more] DC2007-110 CPSY2007-106
pp.155-160
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