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Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
14:10		 Kanagawa   Optimal Design and Performance Evaluation of Residue Arithmetic Circuits with a Binary Coding of Signed-Digit Number
Takuya Kobayashi, Kazuhiro Motegi, Shugang Wei (Gunma Univ.) VLD2012-114 CPSY2012-63 RECONF2012-68		 Signed-Digit (SD) has a redundancy by using \{-1,0,1\}.
By applying the redundant binary representation to arithmetic c... [more]		 VLD2012-114 CPSY2012-63 RECONF2012-68
pp.39-44
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
14:35		 Kanagawa   Design and Performance Evaluation of RSA Encryption Processor Using Signed-Digit Number Arithmetic
Junichi Asaoka, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2012-115 CPSY2012-64 RECONF2012-69		 RSA encryption processing spends a lot of time on modular exponentiation of long word length, therefore the speed of the... [more] VLD2012-115 CPSY2012-64 RECONF2012-69
pp.45-50
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-26
11:15		 Kanagawa Hiyoshi Campus, Keio University Error Checker using Binary tree structure of Residue Signed-Digit Additions
Qian Liu, Kazuhiro Motegi, Shugang Wei (Gunma Univ.) VLD2011-111 CPSY2011-74 RECONF2011-70		 In this paper, a fast residue checker for error detection of arithmetic circuits is presented. The residue checker consi... [more] VLD2011-111 CPSY2011-74 RECONF2011-70
pp.117-121
CPSY, VLD, IPSJ-SLDM 2005-01-26
17:20		 Kanagawa   Architecture of RNS to Mixed-Radix Number Converter Using Signed-Digit Number Arithmetic
Yumi Ogawa, Shuangching Chen, Shugang Wei (Gunma Univ.) 		By introducing a signed-digit(SD) number arithmetic into a residue number system (RNS), arithmetic operations can be per... [more] VLD2004-123 CPSY2004-89
pp.79-84
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