Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
MBE, NC (Joint) |
2022-03-03 14:40 |
Online |
Online |
Designing a Brain Reference Architecture for Double Articulation Analyzer of Spoken Language Maoko Muro, Akira Taniguchi (Ritsumeikan), Hiroshi Yamakawa (WBAI/UTokyo/RIKEN), Tadahiro Taniguchi (Ritsumeikan) NC2021-64 |
In human spoken language, words are connected to form a sentence, and words are composed of phonemes or syllables. This ... [more] |
NC2021-64 pp.94-99 |
ICD |
2016-04-14 15:15 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
[Invited Lecture]
1T1MTJ STT-MRAM Cell Array Design with an Adaptive Reference Voltage Generator Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Tosinari Watanabe, Hideo Sato, Soshi Sato, Takashi Nasuno, Yasuo Noguchi, Mitsuo Yasuhira, Takaho Tanigawa, Masaaki Niwa, Kenchi Ito, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh (Tohoku Univ.) ICD2016-10 |
A device-variation-tolerant spin-transfer-torque magnetic random access memory (STT-MRAM) cell array with a high-signal-... [more] |
ICD2016-10 pp.51-56 |
RECONF |
2013-09-19 14:50 |
Ishikawa |
Japan Advanced Institute of Science and Technology |
Considerations of Constantize for Entries in Associative Memories Using Dynamic Partial Reconfiguration Tomoaki Ukezono, Koichi Araki (JAIST) RECONF2013-36 |
In general, memories which can be referenced by associative search will enlarge hardware size and extend delay for refer... [more] |
RECONF2013-36 pp.97-102 |
ICD |
2013-04-12 12:00 |
Ibaraki |
Advanced Industrial Science and Technology (AIST) |
[Invited Lecture]
An Integrated Variable Positive/Negative Temperature Coefficient Read Reference Generator for MLC PCM/NAND Hybrid 3D SSD Kousuke Miyaji, Koh Johguchi (Chuo Univ.), Kazuhide Higuchi (Univ. of Tokyo), Ken Takeuchi (Chuo Univ.) ICD2013-17 |
An integrated variable temperature coefficient (TC) reference generator for multi-level cell phase change memory (PCM)/N... [more] |
ICD2013-17 pp.85-90 |
EST, EMCJ, IEE-EMC [detail] |
2012-10-26 13:25 |
Miyagi |
Tohoku Gakuin University(Tagajo Campus) |
Calibration of Loop Antennas for EMI Measurements using Reference Antenna Katsumi Fujii (NICT), Masanori Ishii (AIST) EMCJ2012-82 EST2012-66 |
There were two calibration methods of loop antennas for EMI measurements below 30 MHz using reference antenna of which m... [more] |
EMCJ2012-82 EST2012-66 pp.109-114 |
ICD |
2010-04-22 15:45 |
Kanagawa |
Shonan Institute of Tech. |
A 32-Mb SPRAM with localized bi-directional write driver, '1'/'0' dual-array equalized reference scheme, and 2T1R memory cell layout Riichiro Takemura, Takayuki Kawahara, Katsuya Miura, Hiroyuki Yamamoto, Jun Hayakawa, Nozomu Matsuzaki, Kazuo Ono, Michihiko Yamanouchi, Kenchi Ito, Hiromasa Takahashi (Hitachi), Shoji Ikeda (Tohoku Univ.), Haruhiro Hasegawa, Hideyuki Matsuoka (Hitachi), Hideo Ohno (Tohoku Univ.) ICD2010-10 |
A 32-Mb SPin-transfer torque RAM (SPRAM) chip was demonstrated with an access time of 32 ns and a cell write-time of 40 ... [more] |
ICD2010-10 pp.53-57 |
ICD |
2009-12-14 13:30 |
Shizuoka |
Shizuoka University (Hamamatsu) |
[Poster Presentation]
Intermittent Pulse Generator for Ultra-Low Power LSIs Hiromichi Matsushita, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya (Hokkaido Univ.) ICD2009-89 |
We proposed a timer circuit for the intermittent operation of ultra-lowpower LSIs. The circuit consists of a clock oscil... [more] |
ICD2009-89 pp.65-70 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 11:20 |
Kochi |
Kochi City Culture-Plaza |
A Reference CMOS Circuit Structure for Evaluation of Power Supply Noise Tetsuro Matsuno, Daisuke Kosaka (Kobe Univ.), Makoto Nagata (Kobe Univ./ CREST-JST) CPM2009-137 ICD2009-66 |
Accurate understandings of dynamic noises in power delivery networks of very large scale integration (VLSI) chips are st... [more] |
CPM2009-137 ICD2009-66 pp.19-22 |
ICD, ITE-IST |
2009-10-02 17:25 |
Tokyo |
CIC Tokyo (Tamachi) |
A fully-integrated clock reference generator with frequency-locked loop Ken Ueno, Tetsuya Asai, Yoshihito Amemiya (Hokkaido Univ.) ICD2009-61 |
A temperature- and supply-independent clock generator has been developed using 0.35-um CMOS technology. This generator i... [more] |
ICD2009-61 pp.159-164 |
CAS, NLP |
2009-09-25 11:00 |
Hiroshima |
Hiroshima Univ. Higashi Senda Campus |
Associative-Memory-Based LSI Architecture with Automatic Learning Functionality and Application to Handwritten-Character Recognition Wataru Imafuku, Tania Ansari, Akio Kawabata, Hans Juergen Mattausch, Tetsushi Koide (Hiroshima Univ.) CAS2009-40 NLP2009-76 |
n the presented research on VLSI-system design for handwritten-character learning and recognition, an associative memory... [more] |
CAS2009-40 NLP2009-76 pp.91-96 |
ICD, ITE-IST |
2008-10-22 17:30 |
Hokkaido |
Hokkaido University |
An Ultra-low Power Voltage Reference consisting of Subthreshold MOSFETs Ken Ueno (Hokkaido Univ.), Tetsuya Hirose (Kobe Univ.), Tetsuya Asai, Yoshihito Amemiya (Hokkaido Univ.) ICD2008-68 |
An ultra-low power CMOS voltage reference circuit has been fabricated in
0.35-um standard CMOS process. The circuit ge... [more] |
ICD2008-68 pp.55-60 |
SDM, ED |
2008-07-11 14:35 |
Hokkaido |
Kaderu2・7 |
A Novel 800mV Reference Current Source Circuit for Low-Power Low-Voltge Mixed-Mode Systems Oh Jun Kwon, Kae DalKwack (Hanyang Univ.) ED2008-94 SDM2008-113 |
In this paper, a novel beta-multiplier reference current source circuit for the 800mV power-supply voltage is presented.... [more] |
ED2008-94 SDM2008-113 pp.291-293 |
ICD, ITE-IST |
2007-07-26 08:55 |
Hyogo |
|
CMOS voltage reference based on threshold voltage of a MOSFET Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya (Hokkaido Univ.) ICD2007-38 |
We developed a voltage reference circuit using MOSFETs operated in the subthreshold region, except for the MOS resistor ... [more] |
ICD2007-38 pp.5-10 |
ICD, ITE-IST |
2007-07-26 09:20 |
Hyogo |
|
A Trimming-Free CMOS Bandgap-Reference Circuit with Sub-1-V-Supply Voltage Operation Yuichi Okuda, Takayuki Tsukamoto, Mitsuru Hiraki, Masashi Horiguchi, Takayasu Ito (Renesas) ICD2007-39 |
We propose a bandgap-reference circuit (BGR) that is very robust against voltage, temperature, and local device variatio... [more] |
ICD2007-39 pp.11-15 |
MW, ED |
2007-01-19 09:45 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
A 2.4-V Reference Voltage Operation InGaP-HBT MMIC Power Amplifier for CDMA Handsets Takao Moriwaki, Kazuya Yamamoto, Nobuyuki Ogawa, Takeshi Miura, Kosei Maemura, Teruyuki Shimura (Mitsubishi Electric) |
This paper describes circuit design and measurement results of a newly developed InGaP/GaAs HBT MMIC power amplifier mod... [more] |
ED2006-226 MW2006-179 pp.143-148 |
EE |
2006-07-14 09:30 |
Tokyo |
|
Control Strategy of Digitally Controlled DC-DC Converter with Static Model Koji Tanaka, Fujio Kurokawa (Nagasaki Univ.), (Choryo Control System), Hirofumi Matsuo (Nagasaki Univ.) EE2006-17 |
The digitally controlled dc-dc converter with static model reference has been proposed to improve the dynamic characteri... [more] |
EE2006-17 pp.47-52 |
EA |
2006-03-13 09:00 |
Tokyo |
|
On a difference between the sound quality generated by vacuum tube and that by FET amplifier
-- Why people prefer the sound of vacuum tube to that of FET -- Naoki Otsuka, Masanori Kimoto, Haruo Hirose (NIT) |
Some people insist that there exists a difference between music sounds generated by a vacuum tube amplifier and that by ... [more] |
EA2005-104 pp.1-4 |
EE |
2005-11-11 17:15 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Power factor-corrective circuit without sine-wave reference Koichi Morita (Office Morita) |
As the limits for harmonic current emission was enshrined into law and many countries started to adopt it. So with the p... [more] |
EE2005-46 pp.43-46 |