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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF | 2023-08-04 14:55 |
Hokkaido | Hakodate Arena (Primary: On-site, Secondary: Online) |
An Elastic FPGA-based Accelerator for Bayesian Network Structure Learning Ryota Miyagi (The Univ. of Tokyo), Ryota Yasudo (Kyoto Univ.), Kentaro Sano (RIKEN), Hideki Takase (The Univ. of Tokyo)  RECONF2023-15 |
A Bayesian network is a powerful model for representing knowledge involving uncertainty within discrete random variables... [more] | RECONF2023-15 pp.7-12 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-01 10:35 |
Online | Online | Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops Aika Kamei, Takuya Kojima, Hideharu Amano (Keio Univ.), Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami (SIT), Keizo Hiraga, Kenta Suzuki (SSS) VLD2021-20 ICD2021-30 DC2021-26 RECONF2021-28 |
IoT and edge-computing have been attracting much attention and demands for power efficiency as well as high performance ... [more] | VLD2021-20 ICD2021-30 DC2021-26 RECONF2021-28 pp.19-24 |
| RECONF | 2021-09-10 15:00 |
Online | Online | Parallel Calculation of Local Scores in Bayesian Network Structure Learning using FPGA Ryota Miyagi (Kyoto Univ.), Hideki Takase (U. Tokyo/JST) RECONF2021-22 |
Bayesian network (BN) is a directed acyclic graph that represents relationships among variables in data sets. Because le... [more] | RECONF2021-22 pp.30-35 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 09:25 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Ultra Low Power Reconfigurable Accelerator CC-SOTB2 Koichiro Masuyama, Naoki Ando, Yusuke Matsushita, Hayate Okuhara, Hideharu Amano (Keio Univ.) VLD2016-54 DC2016-48 |
Cool mega array (CMA) is a low power coarse-grained reconfigurable accelerator developed using silicon on thin BOX (SOTB... [more] | VLD2016-54 DC2016-48 pp.61-66 |
| CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] | 2015-03-07 08:30 |
Kagoshima | Power optimization of low-power reconfigurable accelerator CMA-SOTB Yu Fujita, Hayate Okuhara, Koichiro Masuyama, Hideharu Amano (Keio Univ.) CPSY2014-174 DC2014-100 |
(To be available after the conference date) [more] | CPSY2014-174 DC2014-100 pp.71-76 |
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| RECONF | 2014-06-12 11:40 |
Miyagi | Katahira Sakura Hall | Body bias control of low-power reconfigurable accelerator CMA-SOTB Yu Fujita, Hongliang Su, Hideharu Amano (Keio univ.) RECONF2014-8 |
For low power yet high performance processing in battery driven devices, a coarse grained reconfigurable accelerator cal... [more] | RECONF2014-8 pp.37-42 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 08:55 |
Kagoshima | Mapping of Java bytecode to virtual CGRA with implementation in FPGA Yuki Ogawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2013-47 |
In embedded systems, the needs for rapid both low-cost development and high performance has been increasing recently. ... [more] |
RECONF2013-47 pp.45-50 |
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| RECONF | 2013-09-18 17:00 |
Ishikawa | Japan Advanced Institute of Science and Technology | A Restricted Dynamically Reconfigurable Architecture for Low Power Processors Takeshi Hirao, Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura (Hokkaido Univ.) RECONF2013-24 |
Reconfigurable processors have widely attracted attention as an approach to realize high-performance and highly energy-e... [more] | RECONF2013-24 pp.25-30 |
| RECONF | 2013-09-19 09:00 |
Ishikawa | Japan Advanced Institute of Science and Technology | A Low power Reconfigurable Accelerator using a Back-gate Bias Control Technique Hongliang Su, Weihan Wang, Hideharu Amano (Keio Univ.) RECONF2013-26 |
Leakage power is a serious problem especially for accerelators which use a large size Processing Ele- ment (PE) array. H... [more] | RECONF2013-26 pp.37-42 |
| RECONF | 2013-05-20 16:25 |
Kochi | Kochi Prefectural Culture Hall | Speed-up of Dynamically Reconfigurable Processor Array Toru Katagiri, Hideharu Amano (Keio Univ.) RECONF2013-5 |
In order to achieve a high performance on the Dynamically Reconfigurable Processor Array (DRPA), it is common to increas... [more] | RECONF2013-5 pp.25-30 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] | 2013-03-14 09:10 |
Nagasaki | Guarantee of finising of calculate for a low power accelerator CMA Akihito Tsusaka, Mai Izawa, Rie Uno, Nobuaki Ozaki, Hideharu Amano (Keio Univ.) CPSY2012-86 DC2012-92 |
Cool Mega-Array (CMA) is a novel high performance but low power reconfigurable accelerator consisting of a large PE (Pr... [more] |
CPSY2012-86 DC2012-92 pp.205-210 |
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| IE, SIP, ICD, VLD, IPSJ-SLDM [detail] | 2012-10-19 13:00 |
Iwate | Hotel Ruiz | Accelerator Architecture for Multi Scale Filter Operation Shinya Ueno, Gauthier Lovic Eric, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) VLD2012-51 SIP2012-73 ICD2012-68 IE2012-75 |
Image recognition processing includes a number of filter operations which dominate the total execution time. Exploiting... [more] |
VLD2012-51 SIP2012-73 ICD2012-68 IE2012-75 pp.59-64 |
| DC, CPSY (Joint) |
2012-08-02 16:15 |
Tottori | Torigin Bunka Kaikan | Co-processor of a low power accelerator CMA Mai Izawa, Nobuaki Ozaki, Yusuke Koizumi, Rie Uno, Hideharu Amano (Keio Univ.) CPSY2012-14 |
Cool Mega-Array (CMA) is a novel high performance but low power reconfigurable accelerator consisting of a large PE(Proc... [more] | CPSY2012-14 pp.31-36 |
| RECONF | 2012-05-29 10:35 |
Okinawa | Tiruru (Naha Okinawa, Japan) | A study on memory controller of MuCCRA-3: Dynamically Reconfigurable Processor Array Toru Katagiri, Kazuei Hironaka, Hideharu Amano (Keio Univ.) RECONF2012-4 |
In order to achieve a high performance on the Dynamically Reconfigurable Processor Array(DRPA), it is necessary to use P... [more] | RECONF2012-4 pp.19-24 |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-24 14:20 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | Three-Dimensional Accelerator Architecture for Image Recognition Shinya Ueno, Gauthier Lovic Eric, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) SIP2011-63 ICD2011-66 IE2011-62 |
Image recognition used widely in several areas needs high-performance and low power processor. Accelerator is an effecti... [more] | SIP2011-63 ICD2011-66 IE2011-62 pp.7-12 |
| RECONF | 2011-09-26 10:45 |
Aichi | Nagoya Univ. | Wavepipelining on A Ultra Low Power Reconfigurable Accelerator CMA-1. Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. of Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (The Univ. of Electro-Communications) RECONF2011-22 |
CMA(Cool Mega-Array)-1 is a prototype media accelerator consisting of a large PE array which includes 24bit 8 × 8 PEs wi... [more] | RECONF2011-22 pp.1-6 |
| RECONF | 2011-05-13 10:45 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Optimization of Application Programs of SLD-1 : A Low Power Accelarator Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Tech. Univ.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Tokyo Univ. of Electro-Communication) RECONF2011-15 |
SLD(Silent Large Datapath)-1 is a prototype media accelerator consisting of a large PE array which includes 24bit 8 × 8 ... [more] | RECONF2011-15 pp.85-90 |
| RECONF | 2011-05-13 11:10 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Implementation and Evaluation of a low power accelerator SLD-2 Mai Izawa, Nobuaki Ozaki, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano (Keio Univ.) RECONF2011-16 |
Silent Large Datapath or SLD is a novel high performance but low power accelerator architecture for battery driven mobil... [more] | RECONF2011-16 pp.91-96 |
| ICD, IPSJ-ARC | 2011-01-21 11:40 |
Kanagawa | Keio University (Hiyoshi Campus) | Acceleration of Block Matching by using Multiple Alignments on Heterogeneous Multi-Core Processor Yoshitaka Hiramatsu (Hitachi), Hasitha Muthumala Waidyasooriya, Masanori Hariyama (Tohoku Univ.), Tohru Nojiri, Kunio Uchiyama (Hitachi) |
The large data-transfer time among different cores and data-supply time to arithmetic unit is a big problem in heterogen... [more] | ICD2010-136 pp.57-62 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 14:30 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Implementation of Dynamic Reconfigurable Processor with Multi-Accelerator Shuhei Igari, Junji Kitamichi, Yuichi Okuyama, Kenichi Kuroda (Aizu Univ.) VLD2010-108 CPSY2010-63 RECONF2010-77 |
Recently, System on a Chip (SoC) has problems increasing of the scale of circuit and design cost, because SoC contains m... [more] | VLD2010-108 CPSY2010-63 RECONF2010-77 pp.163-168 |
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