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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2022-03-01 13:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Primary: On-site, Secondary: Online) |
A Logic Locking Method based on SFLL-hd at Register Transfer Level Yohei Noguchi, Masayoshi Yoshimura (Kyoto Sangyo Univ.), Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.)  DC2021-72 |
In recent years, with the increase of VLSI integration, LSI design companies utilize circuit design information, called ... [more] | DC2021-72 pp.45-50 |
| VLD, HWS (Joint) |
2018-02-28 13:55 |
Okinawa | Okinawa Seinen Kaikan | Congestion Aware High Level Synthesis Design Flow with Source Compiler Masato Tatsuoka, Mineo Kaneko (JAIST) VLD2017-96 |
When we use a high level synthesis (HLS) tool, the optimization of input code is necessary for obtaining an optimized ... [more] | VLD2017-96 pp.43-48 |
| DC | 2017-02-21 14:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Impact of Operational Unit Binding on Aging-induced Degradation in High-level Synthesis for Asynchronous Systems Tsuyoshi Iwagaki, Kohta Itani, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2016-78 |
This paper discusses delay-robustness of a four-phase dual-rail asynchronous system at register transfer level (RTL). A ... [more] | DC2016-78 pp.23-28 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 17:30 |
Oita | B-ConPlaza | A Hardware Trojans Detection Method focusing on Nets in Hardware Trojans in Gate-Level Netlists Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-91 DC2014-45 |
Recently, digital ICs are designed by outside vendors to reduce design costs in semiconductor industry. This circumstan... [more] |
VLD2014-91 DC2014-45 pp.135-140 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 14:45 |
Oita | B-ConPlaza | A Study of Power Optimization for Asynchronous Circuits with Bundled-data Implementation using Mobility of Operations Shunya Hosaka, Hiroshi Saito (Univ. Aizu) VLD2014-104 DC2014-58 |
In this paper, we study a dynamic power optimization method for asynchronous circuits with bundled-data implementation u... [more] | VLD2014-104 DC2014-58 pp.215-220 |
| VLD | 2014-03-05 15:20 |
Okinawa | Okinawa Seinen Kaikan | Function Code Extraction from RTL Property for Reuse Msaato Tatsuoka, Toshiaki Aoki, Mineo Kaneko (JAIST) VLD2013-165 |
RTL Property is frequently reused in the RTL design, but its re-optimization for a target advanced process technology is... [more] | VLD2013-165 pp.171-176 |
| VLD | 2013-03-05 10:50 |
Okinawa | Okinawa Seinen Kaikan | High Level Resynthesis Approach of Reusable RTL Property Msaato Tatsuoka, Mineo Kaneko (JAIST) VLD2012-145 |
Similar to RTL language that has been used as a design entry for LSI, a high-level description language such as SystemC,... [more] | VLD2012-145 pp.55-60 |
| RCS | 2012-06-21 15:00 |
Hokkaido | Hakodate City Central Library | Hardware Design of 1.3Gbps Multi-User MIMO System for IEEE802.11ac Leonardo Lanante, Shogo Fujita, Yuji Yokota, Yuhei Nagao, Masayuki Kurosaki, Hiroshi Ochi (Kyushu Inst. of Tech.) RCS2012-74 |
We present our hardware design of a very high throughput Multi-user Multiple Input Multiple Output (MU-MIMO) wireless LA... [more] | RCS2012-74 pp.181-186 |
| DC | 2009-06-19 13:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
High-level Design for Test Tools & Industrial Design Flows Chouki Aktouf (DeFacTo) DC2009-14 |
Design for Testability at Register Transfer Level has been widely explored by academia. Commercial tools start to be co... [more] |
DC2009-14 pp.25-28 |
| SIS | 2008-03-13 12:50 |
Tokyo | Musashi Institute of Technology(Setagaya) | PHY and MAC layer design for 600Mbps MIMO wireless LAN system Akihiro Teramoto, Tomohiko Oka, Tadashi Maemura, Ryuta Imashioya, Yuhei Nagao, Baiko Sai, Masayuki Kurosaki, Hiroshi Ochi (Kyushu Inst. of Tech.) SIS2007-71 |
In recent years, MIMO technology has become an important to wireless communication systems because it makes high-speed, ... [more] | SIS2007-71 pp.17-22 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-21 15:45 |
Fukuoka | Kitakyushu International Conference Center | Architecture Exploration Method for Low-Power Dynamically Reconfigurable Processors Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbungheng, Hideharu Amano (Keio Univ.) RECONF2007-40 |
In this paper, we propose a design and evaluation environment for exploring the configurable dynamically reconfigurable ... [more] | RECONF2007-40 pp.25-30 |
| SIP, SIS, SP | 2007-09-28 10:30 |
Aichi | Nagoya Inst. of Tech. | Design of Single Carrier Wireless System with Frequency Domain Equalizer Kunitoshi Nishijo, Wahyul Amien Syafei, Masayuki Kurosaki, Hiroshi Ochi (Kyushu Inst. of Tech.) SIP2007-97 SIS2007-33 SP2007-59 |
In this paper, we present a single carrier (SC) wireless system with a frequency domain equalizer (FDE) to overcome th... [more] |
SIP2007-97 SIS2007-33 SP2007-59 pp.13-16 |
| RCS, MoNA, WBS, SR, MW (Joint) |
2007-03-07 13:00 |
Kanagawa | YRP | IP Design for Next Generation Wireless LAN System LSI Yuhei Nagao, Kohta Higashi, Yuuki Yamanaka, Masayuki Kurosaki (Kyushu Inst. of Tech.), Hiroshi Ochi (Radrix) RCS2006-243 |
In this paper, we present several IP designs for next generation wireless LAN system LSI complying with standard IEEE802... [more] | RCS2006-243 pp.33-36 |
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