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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 11 of 11  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF 2020-05-29
15:05
Online Online A tightly-connected RISC-V manycore processor in a SIMD manner
Tan Yuxi, Riadh Ben Abdelhamid, Yoshiki Yamaguchi (Tsukuba Univ.) RECONF2020-17
The size and complexity of scientific and industrial applications have grown larger with computational technology develo... [more] RECONF2020-17
pp.91-96
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-23
11:50
Kanagawa Raiosha, Hiyoshi Campus, Keio University Binary Synthesis from RISC-V Executables
Shoki Hamana, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2019-71 CPSY2019-69 RECONF2019-61
This article presents a method of synthesizing hardware from RISC-V binary codes. RISC-V is an open source instruction s... [more] VLD2019-71 CPSY2019-69 RECONF2019-61
pp.111-115
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-23
13:30
Kanagawa Raiosha, Hiyoshi Campus, Keio University Design and implementation of a RISC-V computer system running Linux in Verilog HDL
Junya Miura, Hiromu Miyazaki, Kenji Kise (Tokyo Tech) VLD2019-72 CPSY2019-70 RECONF2019-62
RISC-V is an instruction set architecture developed at the University of California, Berkeley.
Processors using RISC-V ... [more]
VLD2019-72 CPSY2019-70 RECONF2019-62
pp.117-122
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-23
13:55
Kanagawa Raiosha, Hiyoshi Campus, Keio University Design and implementation of a RISC-V soft processor adopting five-stage pipelining
Hiromu Miyazaki, Takuto Kanamori, Md Ashraful Islam, Kenji Kise (Tokyo Tech) VLD2019-73 CPSY2019-71 RECONF2019-63
In this paper, we propose a RISC-V soft processor adopting five-stage pipelining optimized for FPGAs that support RV32I,... [more] VLD2019-73 CPSY2019-71 RECONF2019-63
pp.123-128
CPSY, DC, IPSJ-ARC [detail] 2019-07-24
13:30
Hokkaido Kitami Civic Hall Proposal of Scalable Vector Instruction Set for Embedded RISC-V Processor
Yoshiki Kimura, Tomoya Kikuchi, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.) CPSY2019-18 DC2019-18
Recently, the use of FPGA in the embedded field has increased. However, development using FPGA is high development costs... [more] CPSY2019-18 DC2019-18
pp.21-26
RECONF 2019-05-09
12:35
Tokyo Tokyo Tech Front Efficient Instruction Fetch Architectures for a RISC-V Soft Processor
Hiromu Miyazaki, Junya Miura, Kenji Kise (Tokyo Tech) RECONF2019-1
We aim to develop a cost-effective RISC-V scalar processor of pipelining for FPGAs. In this report, we try to implement ... [more] RECONF2019-1
pp.1-6
CPSY, DC, IPSJ-ARC
(Joint) [detail]
2018-07-30
14:30
Kumamoto Kumamoto City International Center Proposition and Implementation of RISC-V Processor with Data path extension for 10G Ethernet
Yosuke Yanai, Takeshi Matsuya, Yohei Kuga, Tokusashi Yuta, Jun Murai (Keio Univ.) CPSY2018-15
In this paper, we propose a processor with 1024 bit wide data path for packet processing. A software packet processing e... [more] CPSY2018-15
pp.33-38
RECONF 2017-09-26
14:20
Tokyo DWANGO Co., Ltd. Implementing RISC-V with a Python-Based High-Level Synthesis Compiler
Ryouzaburo Suzuki, Hiroaki Kataoka (Sinby) RECONF2017-36
During the last decade, the environment of field-programmable gate array (FPGA) development has changed rapidly, and the... [more] RECONF2017-36
pp.81-86
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2016-03-24
15:40
Nagasaki Fukue Bunka Hall/Rodou Fukushi Center Design and Implementation of VM Secure Processor for Cloud Forensics
Takuya Chida, Hiroki Taniai, Mizuki Miyanaga, Hidetsugu Irie, Shuichi Sakai (UTokyo) CPSY2015-143 DC2015-97
(To be available after the conference date) [more] CPSY2015-143 DC2015-97
pp.115-120
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-29
14:35
Kagoshima   A Study on the Design of Processor System for Stream Processing
Yusuke Sekihara, Koji Yamazaki, Akihiko Miyazaki (NTT) VLD2013-101 DC2013-67
Processing performance required for packet data transfer system has been improving year by year due to the high-speed da... [more] VLD2013-101 DC2013-67
pp.287-292
IE, SIP, ICD, IPSJ-SLDM 2004-10-22
11:15
Yamagata   Low-Latency and Small-Code-Size Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications
Yasuo Sugure (Hitachi), Seiji Takeuchi (Renesas), Yuichi Abe, Hiromichi Yamada (Hitachi), Kazuya Hirayanagi, Akihiko Tomita, Kesami Hagiwara, Takeshi Kataoka (Renesas), Takanori Shimura (Hitachi)
A 32-bit embedded RISC microcontroller core targeted for automotive, industrial, and PC-peripheral applications has been... [more] SIP2004-93 ICD2004-125 IE2004-69
pp.25-30
 Results 1 - 11 of 11  /   
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