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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2024-03-22 09:25 |
Nagasaki | Ikinoshima Hall (Primary: On-site, Secondary: Online) |
A Design of RISC-V SMT Processor for Real-time Systems Yuta Nojiri, Nobuyuki Yamasaki (Keio Univ.)  CPSY2023-42 DC2023-108 |
Embedded system is used in various regions from home appliances to automobiles. Especially, embedded systems with time c... [more] | CPSY2023-42 DC2023-108 pp.24-28 |
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2024-03-22 09:50 |
Nagasaki | Ikinoshima Hall (Primary: On-site, Secondary: Online) |
Integration of Vector Extension and Simultaneous Multithreading for a RISC-V Processor Hidetaro Tanaka, Shogo Takata, Hironori Nakajo (TUAT) CPSY2023-43 DC2023-109 |
In vector architectures, the potential for parallel execution lies in the chaining of instruction sequences. However, a ... [more] | CPSY2023-43 DC2023-109 pp.29-34 |
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2024-03-22 10:15 |
Nagasaki | Ikinoshima Hall (Primary: On-site, Secondary: Online) |
Context Cache Design for Multicore RISC-V Processors Akira Yamazawa (Keio Univ), Tsutomu Itou, Suito Kazutoshi (AXELL), Nobuyuki Yamasaki (Keio Univ) CPSY2023-44 DC2023-110 |
Today, programs are executed using multiple threads. When multiple threads are used for execution, a context switch occu... [more] | CPSY2023-44 DC2023-110 pp.35-40 |
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2024-03-23 09:50 |
Nagasaki | Ikinoshima Hall (Primary: On-site, Secondary: Online) |
An Efficient and Secure Data Transfer Method for Large Data between Host and Enclave on Keystone Enclave Akihiro Saiki, Keiji Kimura (Waseda Univ.) CPSY2023-49 DC2023-115 |
Keystone Enclave, one of the TEE implementations in RISC-V, lacks flexibility in data transfer between the host and the ... [more] | CPSY2023-49 DC2023-115 pp.65-70 |
| VLD, HWS, ICD | 2024-02-29 11:15 |
Okinawa | (Primary: On-site, Secondary: Online) |
Design of RISC-V SoC with Post-quantum Encryption Algorithm Acceleration Jiyuan Xin, Makoto Ikeda (UTokyo) VLD2023-110 HWS2023-70 ICD2023-99 |
The foundational elements of the Internet of Things (IoT) are increasingly intricate and robust Systems-on-Chips (SoCs) ... [more] | VLD2023-110 HWS2023-70 ICD2023-99 pp.66-71 |
| RECONF, VLD | 2024-01-29 10:30 |
Kanagawa | AIRBIC Meeting Room 1-4 (Primary: On-site, Secondary: Online) |
Random number generation on the Rocket core with a built-in LFSR Takayoshi Shikano, Shuichi Ichikawa (Toyohashi Tech.) VLD2023-80 RECONF2023-83 |
Masaoka et al. developed an unpredictable random number generator (URNG) using a built-in linear feedback shift register... [more] | VLD2023-80 RECONF2023-83 pp.1-6 |
| RECONF, VLD | 2024-01-30 13:45 |
Kanagawa | AIRBIC Meeting Room 1-4 (Primary: On-site, Secondary: Online) |
Implementation of External Memory Access for Binary Synthesis Using General-Purpose High-Level Synthesizer Sho Kishimoto, Nagisa Ishiukra (Kwansei Gakuin Univ.) VLD2023-95 RECONF2023-98 |
In this article, we present a method for implementing external memory access within the context of binary synthesis util... [more] | VLD2023-95 RECONF2023-98 pp.87-92 |
| RECONF | 2023-09-14 16:20 |
Tokyo | Tokyo University of Agriculture and Technology Koganei campus (Primary: On-site, Secondary: Online) |
Integrating RISC-V Vector Extension and SMT for Embedded AI Workloads Hidetaro Tanaka, Shogo Takata, Hironori Nakajo (TUAT) RECONF2023-22 |
In this paper, we plan to implement a processor that accelerates AI workloads by integrating RISC-V vector extensions th... [more] | RECONF2023-22 pp.13-14 |
| RECONF | 2023-09-14 16:40 |
Tokyo | Tokyo University of Agriculture and Technology Koganei campus (Primary: On-site, Secondary: Online) |
Implementation and Evaluation of a Hardware Accelerator using High-Speed Data Transfer with the Vector Register Sharing Mechanism Go Akamatsu, Tomoaki Tanaka (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Kumamoto Univ.), Takefumi Miyoshi (Wasalabo), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT) RECONF2023-24 |
Vector processors can load lots of data and perform operations in parallel. The Vector Register Sharing Mechanism, prop... [more] |
RECONF2023-24 pp.18-19 |
| RECONF | 2023-09-15 13:25 |
Tokyo | Tokyo University of Agriculture and Technology Koganei campus (Primary: On-site, Secondary: Online) |
Implementation and Evaluation of a Hardware Accelerator via Vector Register Sharing Mechanism for Massive Data Transfer Michiya Kato, Tomoaki Tanaka (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Kumamoto Univ.), Takefumi MIyoshi (Wasarabo LLC), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT) RECONF2023-29 |
Vector Register Sharing Mechanism is a method of data transfer by connecting some of the vector registers in the vector ... [more] | RECONF2023-29 pp.40-45 |
| RECONF | 2023-08-04 15:35 |
Hokkaido | Hakodate Arena (Primary: On-site, Secondary: Online) |
Improving Data Transfer Efficiency in Many-Core Systems with a RISC-V ISA Extension Masaru Nishimura, Yuxi Tan, Yoshiki Yamaguchi (Tsukuba Univ.) RECONF2023-16 |
The difficulty of balancing usability and efficient use of PEs and insufficient memory bandwidth are major issues for ma... [more] | RECONF2023-16 pp.13-18 |
| CPSY, DC, IPSJ-ARC [detail] | 2023-08-04 18:20 |
Hokkaido | Hakodate Arena (Primary: On-site, Secondary: Online) |
Power Evaluation of "SLMLET" Chip with Mixed RISC-V MP and SLM Reconfiguration Logic Yosuke Yanai (Keio Univ.), Takuya Kojima (Tokyo Univ./JST PRESTO), Hayate Okuhara (NUS), Hideharu Amano (Keio Univ.), Morihiro Kuga, Masahiro Iida (Kumamoto Univ.) CPSY2023-25 DC2023-25 |
In recent years, opportunities requiring processing at the IoT edge have been increasing. As a solution, not only conven... [more] | CPSY2023-25 DC2023-25 pp.100-105 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-23 16:10 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
VLD2022-61 RECONF2022-84 |
(To be available after the conference date) [more] | VLD2022-61 RECONF2022-84 pp.25-26 |
| MBE, NC | 2022-12-03 15:50 |
Osaka | Osaka Electro-Communication University | A RISC-V Soft-core Processor with Custom VLIW Extension for Spiking Neural Network Accelerator Mingyang Li, Yuki Hayashida (Mie Univ.) MBE2022-40 NC2022-62 |
We aim to develop an embedded accelerator for spiking neural networks (SNN). In order to develop prototypes of various S... [more] | MBE2022-40 NC2022-62 pp.86-91 |
| CPSY, DC, IPSJ-ARC [detail] | 2022-07-28 13:30 |
Yamaguchi | Kaikyo Messe Shimonoseki (Primary: On-site, Secondary: Online) |
Preliminary evaluation of "SLMLET" chip with RISC-V MP and SLM reconfigurable logic Yosuke Yanai (Keio Univ.), Takuya Kojima (Tokyo Univ.), Hayate Okuhara (NUS.), Hideharu Amano (Keio Univ.), Masahiro Iida (Kumamoto Univ.) CPSY2022-8 DC2022-8 |
In recent years, processing power in IoT edge devices has been further improved. Therefore, a solution called a mixed FP... [more] | CPSY2022-8 DC2022-8 pp.41-46 |
| RECONF | 2022-06-07 14:50 |
Ibaraki | CCS, Univ. of Tsukuba (Primary: On-site, Secondary: Online) |
Vector Register Sharing Mechanism for Hardware Acceleration Tomoaki Tanaka, Ryousuke Higashi (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Univ. of the Ryukyus), Takefumi Miyoshi (Wasalabo), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT) RECONF2022-5 |
In this paper, we present a vector register sharing mechanism that directly shares vector registers inside the processor... [more] | RECONF2022-5 pp.26-31 |
| VLD, HWS [detail] | 2022-03-08 15:20 |
Online | Online | Bypassing Isolated Execution on RISC-V Keystone using Fault Injection Shoei Nashimoto, Daisuke Suzuki (Mitsubishi Electric), Rei Ueno, Naofumi Homma (Tohoku Univ.) VLD2021-101 HWS2021-78 |
This paper summarizes an attack and countermeasure against RISC-V Keystone from a paper [1] to be presented at TCHES (IA... [more] | VLD2021-101 HWS2021-78 pp.141-146 |
| ET | 2022-03-04 10:35 |
Online | Online | Development and Operation of a RISC-V Emulator-Based Environment for Distance/BYOD Undergraduate Exercises Tsuneo Nakanishi, Tomoaki Ukezono, Toshifumi Tanabe, Takuya Fujinaga, Tongxin Yang (Fukuoka Univ.) ET2021-52 |
(To be available after the conference date) [more] | ET2021-52 pp.7-12 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 14:50 |
Online | Online | Implementation of a RISC-V SMT Core in Virtual Engine Architecture Hidetaro Tanaka, Tomoaki Tanaka, Keita Nagaoka, Ryosuke Higashi (TUAT), Tsutomu Sekibe, Shuichi Takada (ArchiTek), Hironori Nakajo (TUAT) VLD2021-57 CPSY2021-26 RECONF2021-65 |
The RISC-V core which supports simultaneous multithreading (SMT) on a heterogeneous virtual engine architecture has been... [more] | VLD2021-57 CPSY2021-26 RECONF2021-65 pp.43-48 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-02 14:20 |
Online | Online | Convolutional Neural Network using RISC-V Koki Oshiro (UEC) VLD2021-46 ICD2021-56 DC2021-52 RECONF2021-54 |
(To be available after the conference date) [more] | VLD2021-46 ICD2021-56 DC2021-52 RECONF2021-54 pp.168-171 |
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