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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2020-11-18 09:55 |
Online |
Online |
Column-Parallel Pipelined ADC with Ring Amplifier for High Speed and High Spatial Resolution CMOS Image Sensor Takashi Kojima (TUS), Toshinori Otaka, Yusuke Kameda, Takayuki Hamamoto (TUS) VLD2020-28 ICD2020-48 DC2020-48 RECONF2020-47 |
CMOS image sensor that can capture images with both high time resolution and high spatial resolution is required for ins... [more] |
VLD2020-28 ICD2020-48 DC2020-48 RECONF2020-47 pp.101-105 |
ICD, SDM |
2010-08-26 11:25 |
Hokkaido |
Sapporo Center for Gender Equality |
10bit-300MHz Double-Sampling Pipelined ADC with Digital Calibration for Memory Effects Takuji Miki, Takashi Morie, Toshiaki Ozeki, Shiro Dosho (Panasonic) SDM2010-129 ICD2010-44 |
This paper describes an on-chip digital calibration technique to eliminate a memory effect error in Double-sampling Pipe... [more] |
SDM2010-129 ICD2010-44 pp.29-34 |
ICD, ITE-IST |
2007-07-26 11:10 |
Hyogo |
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The Effects of Switch Resistances on Pipelined ADC Performances and the Optimization for the Settling Time Masaya Miyahara, Akira Matsuzawa (Tokyo Tech.) ICD2007-43 |
In this paper, we discuss the effects of switch resistances on the step response of switched-capacitor circuits, especia... [more] |
ICD2007-43 pp.35-40 |
ICD, VLD |
2007-03-08 16:30 |
Okinawa |
Mielparque Okinawa |
Novel fast digital background calibration for pipelined ADC's Takashi Oshima (Hitachi), Cheonguyrn Tsang, Cheonguyrn Tsang (UC Berkeley) |
The high-speed high-resolution ADC is a key device for the next-generation wireless systems. The digital background cali... [more] |
VLD2006-138 ICD2006-229 pp.115-120 |
ICD |
2005-07-15 13:25 |
Aichi |
Toyohashi Univ. of Tech. |
A 14bit Digitally Self-Calibrated Pipelined ADC with Adaptive Bias Optimization for Arbitrary Speeds up to 40MS/s Hirofumi Matsui, Masaya Ueda, Mutsuo Daito, Kunihiko Iizuka (Sharp) |
A 14bit digitally self-calibrated pipelined ADC featuring the adaptive bias optimization is fabricated in a 0.18μm CMOS ... [more] |
ICD2005-60 pp.31-34 |
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