IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 18 of 18  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, HWS [detail] 2020-10-26
09:25
Online Online Power Analysis Attack Using Pipeline Scheduling on Pairing Hardware
Mitsufumi Yamazaki, Junichi Sakamoto, Tsutomu Matsumoto (YNU) HWS2020-26 ICD2020-15
To reduce the latency of pairing calculation for advanced cryptography, hardware implementations with pipelined modular ... [more] HWS2020-26 ICD2020-15
pp.7-12
ISEC, SITE, ICSS, EMM, HWS, BioX, IPSJ-CSEC, IPSJ-SPT [detail] 2019-07-23
14:25
Kochi Kochi University of Technology Side Channel Security of an FPGA Pairing Implementation with Pipelined Modular Multiplier
Mitsufumi Yamazaki, Junichi Sakamoto, Yuta Okuaki, Tsutomu Matsumoto (YNU) ISEC2019-29 SITE2019-23 BioX2019-21 HWS2019-24 ICSS2019-27 EMM2019-32
Since bilinear pairing is useful in realizing advanced cryptography, side channel security evaluation of its high-speed ... [more] ISEC2019-29 SITE2019-23 BioX2019-21 HWS2019-24 ICSS2019-27 EMM2019-32
pp.151-156
ISEC, SITE, ICSS, EMM, HWS, BioX, IPSJ-CSEC, IPSJ-SPT [detail] 2019-07-23
14:50
Kochi Kochi University of Technology An FPGA Implementation of Aggregate Signature Schemes with Pipelined Modular Multiplier
Yota Okuaki, Junichi Sakamoto, Daisuke Fujimoto, Tsutomu Matsumoto (YNU) ISEC2019-30 SITE2019-24 BioX2019-22 HWS2019-25 ICSS2019-28 EMM2019-33
Expectations for "Advanced Cryptography" are increasing in order to enhance the security of cyber physical systems and c... [more] ISEC2019-30 SITE2019-24 BioX2019-22 HWS2019-25 ICSS2019-28 EMM2019-33
pp.157-162
HWS, ICD 2018-10-29
14:30
Osaka Kobe Univ. Umeda Intelligent Laboratory An Acceleration of Compressed Squaring for Pairing Implementation with Pipeline Modular Multiplier
Yota Okuaki, Junichi Sakamoto, Naoki Yoshida, Daisuke Fujimoto, Tsutomu Matsumoto (YNU) HWS2018-50 ICD2018-42
One of the biggest problems of the emerging cyber-physical and cloud computing systems is how to ensure security with en... [more] HWS2018-50 ICD2018-42
pp.19-24
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-07
10:55
Kumamoto Kumamoto-Kenminkouryukan Parea A Study of Pipelined Hardware Design of Matrix Inversion for Signal Separation in MIMO-OFDM Wireless Communication
Takashi Imagawa (Ritsumeikan Univ.), Takahiro Ikeshita, Hiroshi Tsutsui, Yoshikazu Miyanaga (Hokkaido Univ.) VLD2017-45 DC2017-51
With the increase in the number of MIMO streams and OFDM subcarriers for high-speed wireless communication, the amount o... [more] VLD2017-45 DC2017-51
pp.105-108
IA 2016-11-04
10:55
Overseas Taipei (Taiwan) Real-time Abnormal Traffic Detection Circuit Based on Simple Frequent-Itemset-Mining Method
Shuji Sannomiya, Akira Sato, Kenichi Yoshida (Univ. of Tsukuba) IA2016-47
To resist the growth of abnormal traffic such as P2P flows, DDoS attacks and Internet worms, a circuit design to realize... [more] IA2016-47
pp.93-98
IT, ISEC, WBS 2016-03-10
14:30
Tokyo The University of Electro-Communications A Multiplier Architecture for Finite Field of 254bit-Prime Square Order Based on Pipelined 32bit Montgomery Multipliers
Yusuke Nagahama, Daisuke Fujimoto, Tsutomu Matsumoto (YNU) IT2015-116 ISEC2015-75 WBS2015-99
Bilinear Pairing is a major tool to realize advanced cryptographic functionality such as searchable encryption, aggregat... [more] IT2015-116 ISEC2015-75 WBS2015-99
pp.95-100
DC 2015-06-16
15:35
Tokyo Kikai-Shinko-Kaikan Bldg. A Study on Function Test of Latch-based Asynchronous Pipeline Circuits
Daiki Toyoshima, Kyohei Terayama, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.) DC2015-19
Asynchronous MOUSETRAP pipeline circuit is a simple and fast circuit thanks to the 2-phase handshaking protocol which ha... [more] DC2015-19
pp.19-24
SIS 2014-03-06
11:40
Osaka Gran Front Osaka, Knowledge Capital C-9F, 901 Hardware Implementation of Soft Cascaded SVM Classifier
Kazutaka Takeuchi, Jaehoon Yu (Osaka Univ.), Ryusuke Miyamoto (Meiji Univ.), Takao Onoye (Osaka Univ.) SIS2013-58
To speed up the object detection without degradation of the accuracy, the following two approaches are proposed: Reducin... [more] SIS2013-58
pp.17-22
IPSJ-SLDM, CPSY, RECONF, VLD [detail] 2014-01-29
10:25
Kanagawa Hiyoshi Campus, Keio University Implementation of MuCCRA-4: Dynamically Reconfigurable Processor Array
Toru Katagiri, Hideharu Amano (Keio Univ.) VLD2013-122 CPSY2013-93 RECONF2013-76
Although Dynamically Reconfigurable Processor Arrays (DRPAs) are advantageous for embedded devices because of their high... [more] VLD2013-122 CPSY2013-93 RECONF2013-76
pp.119-124
CPSY 2013-11-08
11:10
Hiroshima   Pipeline Scanning Architecture for Traffic Sign Detection with Computation Reduction
Anh-Tuan Hoang, Masaharu Yamamoto, Mutsumi Omori, Tetsushi Koide (Hiroshima Univ.) CPSY2013-45
This paper describes a novel compact hardware oriented algorithm and its conceptual implementation for real-time traffic... [more] CPSY2013-45
pp.37-42
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-27
10:55
Fukuoka Centennial Hall Kyushu University School of Medicine A Behavioral Synthesis Method for Asynchronous Pipelined Circuits with Bundled-data Implementation
Naohiro Hamada, Hiroshi Saito (The Univ. of Aizu) VLD2012-77 DC2012-43
In this paper, we propose behavioral synthesis methods for asynchronous pipelined circuits with bundled-data implementat... [more] VLD2012-77 DC2012-43
pp.105-110
SIS, IPSJ-AVM 2012-09-20
10:40
Osaka Tottori Pref. Osaka Office A High-Performance Multiplierless Hardware Architecture of the Transform Applied to H.265/HEVC Emerging Video Coding Standard
Wenjun Zhao, Takao Onoye (Osaka Univ.) SIS2012-18
This paper presents a hardware architecture of the transform applied in the emerging video coding standard-HEVC (High Ef... [more] SIS2012-18
pp.11-16
ICD
(Workshop)
2010-08-16
- 2010-08-18
Overseas Ho Chi Minh City University of Technology Review of design methodology for pipelined CPU. Case study: trade-off between pipelined and non-pipelined Little Computer 3
Bui Minh Thanh, Hoang Trang, Ho Trung My (HCMUT)
The review of design methodology for pipelined CPU is presented in this paper. Thanks to high performance, the piplined ... [more]
CPM 2009-08-11
13:55
Aomori Hirosaki Univ. FPGA implementation of a Wave-Pipelined Firewall Unit
Keisuke Saito, Kei Ito, Shuya Imaruoka, Tomoaki Sato, Masa-aki Fukase (Hirosaki Univ.) CPM2009-48
We have been working on the development of H-HIPS by using a FPGA. A FPGA can change circuits information easily. But, i... [more] CPM2009-48
pp.77-81
SIS 2008-06-13
13:15
Hokkaido   An Architecture of Photo Core Transform in HD Photo Coding System for Embedded System of Various Bandwidths
Koichi Hattori (Kyoto Univ.), Hiroshi Tsutsui (Osaka Univ.), Hiroyuki Ochi (Kyoto Univ.), Yukihiro Nakamura (Ritsumeikan Univ.) SIS2008-21
In this paper, we propose a novel architecture of photo core transform (PCT) which is used as transformation of image da... [more] SIS2008-21
pp.39-44
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]
2007-11-21
16:35
Fukuoka Kitakyushu International Conference Center A low power consumption processor with on-chip control mechanism using pipeline stage unification
Katsuya Kimura, Ryotaro Kobayashi, Toshio Shimada (Nagoya Univ.) RECONF2007-42
In this paper, we implement and estimate the low power consumption processor which uses Pipeline Stage Unification (PSU)... [more] RECONF2007-42
pp.37-42
ICD, SDM 2006-08-18
13:45
Hokkaido Hokkaido University [Special Invited Talk] Deep Pipelined SRAM Design for High Performance Processor
Toru Asano (IBM Japan)
Processor performance depends strongly upon SRAM performance. In deep sub-micron technology, increasing device performan... [more] SDM2006-150 ICD2006-104
pp.143-147
 Results 1 - 18 of 18  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan