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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-23 10:30 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Multi-FPGA design environment using Cyberworkbench, a high-level synthesis tool Hiroaki Suzuki (Keio Univ), Wataru Takahashi (NEC), Kazutoshi Wakabayashi (Tokyo Univ), Hideharu Amano (Keio Univ)  VLD2022-56 RECONF2022-79 |
Multi-FPGA systems, in which multiple FPGA boards are directly connected via high-speed serial links, are attracting att... [more] | VLD2022-56 RECONF2022-79 pp.1-6 |
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2020-01-24 14:45 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Partial synthesis method based on Column-wise verification for integer multipliers Jian Gu, Amir Masoud Gharehbaghi, Masahiro Fujita (UTokyo) VLD2019-89 CPSY2019-87 RECONF2019-79 |
Partial logic synthesis is a method that most parts of the target circuits are fixed and the missing portions can be log... [more] | VLD2019-89 CPSY2019-87 RECONF2019-79 pp.211-216 |
| VLD, IPSJ-SLDM | 2018-05-16 13:30 |
Fukuoka | Kitakyushu International Conference Center | Partial logic synthesis by using sum of products or product of sums based quantified boolean formulae Xiaoran Han, Amir Masoud Gharehbaghi, Masahiro Fujita (UTokyo) VLD2018-1 |
documentclass[a4paper,11pt]{jarticle} usepackage{kws} usepackage{amssymb} usepackage{amsmath,array,graphicx} ... [more] |
VLD2018-1 pp.1-5 |
| RECONF | 2015-09-18 14:30 |
Ehime | Ehime University | ZYNQ CLUSTER FOR CFD PARAMETRIC SURVEY Naru Sugimoto, Hideharu Amano (Keio Univ.) RECONF2015-39 |
FaSTAR (Fast Aerodynamics Routines) is a state of the art CFD (Computational Fluid Dynamics) software package to enable ... [more] | RECONF2015-39 pp.39-44 |
| MSS, SS | 2015-01-27 09:20 |
Tottori | A supervisor synthesis by MaxSAT solvers under partial observation Tatsuki Hirota, Shoji Yuen (Nagoya Univ), Tetsuya Tohdo (DENSO) MSS2014-82 SS2014-46 |
Synthesis of the supervisor for discrete event systems under partial observation has been shown exponen- tial in princi... [more] |
MSS2014-82 SS2014-46 pp.79-84 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 09:45 |
Kagoshima | An Area Constraint-Based Fault-Secure HLS Algorithm for RDR Architectures Considering Trade-Off between Reliability and Time Overhead Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-79 DC2013-45 |
With process technology scaling, decreasing reliability caused by soft errors as well as increasing the average intercon... [more] | VLD2013-79 DC2013-45 pp.129-134 |
|
| VLD, IPSJ-SLDM | 2013-05-16 16:00 |
Fukuoka | Kitakyushu International Conference Center | A Zero Time and Area Overhead Fault-Secure High-Level Synthesis Algorithm for RDR Architectures Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-9 |
In this paper, we propose a zero time and area overhead fault-secure high-level synthesis algorithm for RDR architecture... [more] | VLD2013-9 pp.67-72 |
| IPSJ-SLDM, VLD, CPSY, RECONF [detail] | 2010-01-26 17:10 |
Kanagawa | Keio Univ (Hiyoshi Campus) | A Dedicated Functional Unit Synthesis Algorithm with MISO Structures based on Partial Matching Norihiro Hashimoto, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2009-83 CPSY2009-65 RECONF2009-68 |
Requirement for application-specific processor is really increasing recently, however, it takes much time to design a pr... [more] | VLD2009-83 CPSY2009-65 RECONF2009-68 pp.89-94 |
| MSS | 2010-01-22 11:10 |
Aichi | Toyota Central R&D Labs. | Proposal of a Business Process Verification Method using Orders of Tasks Daijiro Murata, Ryota Mibe (Hitachi), Yoshinao Isobe (AIST) CST2009-49 |
To verify upstream design information of an information system, we propose a method transforming partial business proces... [more] | CST2009-49 pp.67-72 |
| MSS | 2009-06-03 10:40 |
Osaka | Setsunan University, Osaka Center | Reinforcement Learning of the Supervisor based on the Worst-Case Behavior Under Partial Observation Kouji Kajiwara, Tatsushi Yamasaki (Setsunan Univ.) CST2009-1 |
In our previous work, we have proposed a synthesis method of the supervisor based on the worst-case behavior of discrete... [more] | CST2009-1 pp.1-6 |
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