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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 11 of 11  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]		 2017-11-07
11:20		 Kumamoto Kumamoto-Kenminkouryukan Parea Implementation and Optimization of Parallel Prefix Adder Using Majority Function
Daiki Matsumoto, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2017-46 DC2017-52		 In recent FPGAs and post CMOS devices, three-input majority operation can be efficiently realized and circuit configuration... [more] VLD2017-46 DC2017-52
pp.109-114
VLD 2017-03-03
11:20		 Okinawa Okinawa Seinen Kaikan Optimization of Parallel Prefix Adder Using Simulated Annealing
Takayuki Moto, Mineo Kaneko (JAIST) VLD2016-127		 In this report, simulated annealing based optimization of parallel prefix adders (PPA) is proposed. In order to construc... [more] VLD2016-127
pp.139-144
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2012-11-28
16:50		 Fukuoka Centennial Hall Kyushu University School of Medicine A Design Method of Fault-Secure Parallel Prefix Adders by Carry-Bit Duplication
Nobutaka Kito (Chukyo Univ.), Naofumi Takagi (Kyoto Univ.) VLD2012-106 DC2012-72		 We show a design method of fault-secure parallel prefix adders with various prefix structures.
Adders by the method gen... [more]		 VLD2012-106 DC2012-72
pp.273-278
CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] 2011-03-18
11:20		 Okinawa   Design Method of Easily Testable Parallel Adders under Delay Constraints
Shinichi Fujii (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.) CPSY2010-75 DC2010-74		 Recently, with the development of VLSI design and manufacturing technology, the scale of integrated circuits on a VLSI c... [more] CPSY2010-75 DC2010-74
pp.57-62
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-UBI, IPSJ-MBL [detail] 2010-03-28
14:35		 Tokyo   A consideration of synthesis methods for easily testable parallel prefix adders
Shinichi Fujii, Naofumi Takagi (Nagoya Univ.) CPSY2009-93 DC2009-90		 Previously, synthesis methods of parallel prefix adders have been proposed. These methods primarily use circuit area and... [more] CPSY2009-93 DC2009-90
pp.489-493
DC 2009-06-19
10:20		 Tokyo Kikai-Shinko-Kaikan Bldg. Design method of easily testable parallel prefix adders
Hidetoshi Suzuki, Naofumi Takagi (Nagoya Univ) DC2009-10		 We propose a design method of easily testable parallel prefix adders. In a parallel prefix adder, the prefix computation... [more] DC2009-10
pp.1-6
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]		 2007-11-22
13:50		 Fukuoka Kitakyushu International Conference Center Parallel prefix adder synthesis based on Ling’s carry computation
Taeko Matsunaga, Shinji Kimura (Waseda Univ.), Yusuke Matsunaga (Kyushu Univ.) 		Ling adders calculate carry propagation based on adjacent bit pairs,
and can be formulated as parallel prefix adders. I... [more]		 VLD2007-97 DC2007-52
pp.49-54
CAS, SIP, VLD 2007-06-22
13:20		 Hokkaido Hokkaido Tokai Univ. （Sapporo) Arithmetic Module Generation Using Optimized Parallel Prefix Adders
Yuki Watanabe, Naofumi Homma, Takafumi Aoki (Tohoku Univ.), Tatsuo Higuchi (Totech) CAS2007-27 VLD2007-43 SIP2007-57		 This paper presents an arithmetic module generator using parallel prefix adders. In the proposed system, parallel prefix... [more] CAS2007-27 VLD2007-43 SIP2007-57
pp.49-54
VLD, IPSJ-SLDM 2007-05-11
11:45		 Kyoto Kyodai Kaikan On power-conscious approach for prefix graph synthesis
Taeko Matsunaga (Waseda Univ), Yusuke Matsunaga (Kyushu Univ.) 		A prefix graph visualizes a global structure of a parallel prefix
adder at technology independent level. Several approa... [more]		 VLD2007-12
pp.31-36
ICD, SIP, IE, IPSJ-SLDM 2006-10-27
09:20		 Miyagi   On synthesis algorithm for parallel prefix adders using dynamic programming
Taeko Matsunaga (FLEETS), Yusuke Matsunaga (Kyushu Univ.) 		This paper addresses parallel prefix adder synthesis which targets area minimization under given timing constraints. Th... [more] SIP2006-102 ICD2006-128 IE2006-80
pp.7-12
VLD, ICD, DC, IPSJ-SLDM 2005-12-01
14:20		 Fukuoka Kitakyushu International Conference Center Consideration on Delay Estimation Methods for Prefix Graphs
Taeko Matsunaga (FLEETS), Yusuke Matsunaga (Kyushu Univ.) 		Prefix graph is an abstract representation of a parallel prefix adder and used to compare characteristics of various typ... [more] VLD2005-69 ICD2005-164 DC2005-46
pp.49-54
 Results 1 - 11 of 11  /   
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