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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IE, CS, IPSJ-AVM [detail] | 2023-12-11 15:30 |
Fukuoka | Kyushu Institute of Technology (Primary: On-site, Secondary: Online) |
[Special Invited Talk]
High-Performance Image Processing Utilizing Hardware Norishige Fukushima (nitech)  CS2023-83 IE2023-25 |
High-speed image signal processing is important to realize applications in various environments. To complete image proc... [more] |
CS2023-83 IE2023-25 p.16 |
| CPSY, IPSJ-ARC, IPSJ-HPC | 2023-12-05 10:55 |
Okinawa | Okinawa Industry Support Center (Primary: On-site, Secondary: Online) |
Performance improvements of Multi-Platform Parallel Computing System Based on Web Technologies Soki Imaizumi, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.) CPSY2023-27 |
Web browsers can be used as architecture-independent execution environments, and nowadays they can provide the same func... [more] | CPSY2023-27 pp.1-6 |
| CPSY, IPSJ-ARC, IPSJ-HPC | 2023-12-06 17:15 |
Okinawa | Okinawa Industry Support Center (Primary: On-site, Secondary: Online) |
An Efficient Sparse Matrix Storage Format for Sparse Matrix-Vector Multiplication and Sparse Matrix-Transpose-Vector Multiplication on GPUs Ryohei Izawa, Yasushi Inoguchi (JAIST) CPSY2023-37 |
The utilization of sparse matrix storage formats is widespread across various fields, including scientific computing, ma... [more] | CPSY2023-37 pp.58-63 |
| NLP | 2023-11-29 10:15 |
Okinawa | Nago city commerce and industry association | Extension of Bifurcation Point Search Application with Parallel NLPSO to Continuous-Time Dynamical Systems Tomo Hasegawa (Tokyo Univ. of Technology), Haruna Matsushita (Kagawa Univ.), Takuji Kousaka (Chukyo Univ.), Hiroaki Kurokawa (Tokyo Univ. of Technology) NLP2023-70 |
This paper reports on the extension of the expansion of the software library for bifurcation point detection via paralle... [more] | NLP2023-70 pp.49-52 |
| EMM, BioX, ISEC, SITE, ICSS, HWS, IPSJ-CSEC, IPSJ-SPT [detail] | 2023-07-24 17:40 |
Hokkaido | Hokkaido Jichiro Kaikan | Statistical Key Recovery Attack Against the Peregrine Lattice-Based Signature Scheme Moeto Suzuki (Kyoto Univ.), Xiuhan Lin (Shandong Univ.), Shiduo Zhang (Tsinghua Univ.), Thomas Espitau (PQShield), Yang Yu (Tsinghua Univ.), Mehdi Tibouchi, Masayuki Abe (NTT) ISEC2023-30 SITE2023-24 BioX2023-33 HWS2023-30 ICSS2023-27 EMM2023-30 |
The Peregrine signature scheme, which is a high-speed variant of Falcon, is one of the candidates in the ongoing Korean ... [more] | ISEC2023-30 SITE2023-24 BioX2023-33 HWS2023-30 ICSS2023-27 EMM2023-30 pp.105-112 |
| SANE | 2023-05-23 09:50 |
Kanagawa | Information Technology R & D Center, MITSUBISHI Electric Corp. (Primary: On-site, Secondary: Online) |
A parallelization of pulse train deinterleaving solver based on variational bayesian method and multiple hypothesis tracking Masato Gocho, Tetsutaro Yamada, Yoshiki Takahashi (Mitsubishi Electric) SANE2023-2 |
On deinterleaving a received pulse-train of multiple source signals, a study of the parallel processing on the GPU-enabl... [more] | SANE2023-2 pp.6-11 |
| HWS | 2023-04-14 13:45 |
Oita | (Primary: On-site, Secondary: Online) |
Fundamental Study on the effect of the Number of RNS Bases on the Side-channel Information Leakage from Modular Multiplier Daisuke Fujimoto, Rikuo Haga, Yuichi Hayashi (NAIST) HWS2023-2 |
In public-key cryptography, the Residue Number System (RNS) has been proposed as a hardware implementation approach that... [more] | HWS2023-2 pp.6-8 |
| NLP, MSS | 2023-03-15 13:40 |
Nagasaki | (Primary: On-site, Secondary: Online) |
Algorithm and Software Investigation for Bifurcation Point Detection via Parallel Nested-Layer Particle Swarm Optimization Tomo Hasegawa (Tokyo Univ. of Technology), Haruna Matsushita (Kagawa Univ.), Takuji Kousaka (Chukyo Univ.), Hiroaki Kurokawa (Tokyo Univ. of Technology) MSS2022-70 NLP2022-115 |
This paper reports on the implementation of an application software for bifurcation point detection that supports parall... [more] | MSS2022-70 NLP2022-115 pp.43-48 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-24 11:45 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Efficient FPGA Implementation of Binarized Neural Networks Based on Generalized Parallel Counter Tree Takahiro Tanigawa, Mugi Noda, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2022-68 RECONF2022-91 |
Binarized neural networks (BNN) allow compact hardware implementation by binarizing weight values and neuron activations... [more] | VLD2022-68 RECONF2022-91 pp.50-55 |
| IE | 2022-01-24 11:10 |
Tokyo | National Institute of Informatics (Primary: On-site, Secondary: Online) |
Efficient dense interpolation of 4D light fields obtained by sparse viewpoints based on depth estimation Hidemichi Yoshino (Tokyo Univ. of Science/NII), Kazuya Kodama (NII), Takayuki Hamamoto (Tokyo Univ. of Science) IE2021-27 |
In order to easily enjoy immersive 3D visual environment reproducing light fields, inexpensive multi-view imaging system... [more] | IE2021-27 pp.1-4 |
| HWS, VLD [detail] | 2021-03-03 13:00 |
Online | Online | [Memorial Lecture]
Scheduling Sparse Matrix-Vector Multiplication onto Parallel Communication Architecture Mingfei Yu, Ruitao Gao, Masahiro Fujita (Univ. Tokyo) VLD2020-71 HWS2020-46 |
There is an obvious trend to make use of hardware including many-core CPU, GPU and FPGA, to conduct computationally inte... [more] | VLD2020-71 HWS2020-46 pp.24-29 |
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2020-01-23 15:25 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | FPGA-based Stream Data Aggregation for Large Sliding-Windows Masaki Osaka (UEC), Masato Yoshimi (TIS), Celimuge Wu, Tsutomu Yoshinaga (UEC) VLD2019-76 CPSY2019-74 RECONF2019-66 |
This paper proposes an FPGA-based Stream Data Aggregation for large Sliding-Windows. We designed Configurable Query Proc... [more] | VLD2019-76 CPSY2019-74 RECONF2019-66 pp.141-146 |
| CPSY, DC, IPSJ-ARC [detail] | 2018-06-15 13:10 |
Yamagata | Takamiya Rurikura Resort | Implementation of Code Generation for Parallel Processing Based on Parallelization Directives in LLVM IR Code Kengo Jingu, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota (Utsunomiya Univ.) CPSY2018-6 DC2018-6 |
Nowadays, multi-core processors are widely used, and the speedup can be accomplished by thread-level parallel processing... [more] | CPSY2018-6 DC2018-6 pp.107-112 |
| QIT (2nd) |
2018-06-04 14:50 |
Hiroshima | ICCH Ran | [Invited Talk]
Physics of Quantum-to-Classical Crossover and Quantum Neural Network Yoshihisa Yamamoto (JST/Stanford Univ.) |
This paper will discuss the novel quantum computing model, dissipative quantum computation, and the physical implementat... [more] | |
| NS | 2018-05-17 13:25 |
Kanagawa | Yokohama City Education Center | Implementation of requesting methods considering sequence control for progressive download using parallel TCP connections Mitsuo Heijo, Junichi Funasaka (Hiroshima City Univ.) NS2018-20 |
When realizing progressive download which replays a video file with simultaneously fetching divided partial les through... [more] | NS2018-20 pp.31-36 |
| SIS | 2018-03-08 15:50 |
Aichi | Meijo Univ. Tempaku Campus | Improvement of Real-time Dehazing Processing Suitable for Embedded Systems Ayaka Yasuda (NIT, Tokuyama Col.), Shota Furukawa (NIT, Kagoshima Col.), Noriaki Suetake (Yamaguchi Univ.), Takanori Koga (NIT, Tokuyama Col.) SIS2017-61 |
Processing for removing haze such as fog and mist superimposed on digital images is called dehazing. When dehazing syste... [more] | SIS2017-61 pp.23-28 |
| CPSY | 2017-11-19 15:00 |
Aomori | Aomori Tourist Information Center, ASPAM | [Poster Presentation]
GPU Applications with Single Kernel Synchronization Technique Shunji Funasaka, Koji Nakano, Yasuaki Ito (Hiroshima Univ.) CPSY2017-56 |
A task array is a 2-dimensional array of tasks with dependency relations. Conventional CUDA implementations repeatedly ... [more] |
CPSY2017-56 pp.33-38 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 09:00 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch Tetsuaki Fujimoto (Ritsumeikan Univ.), Wataru Takahashi, Kazutoshi Wakabayashi (NEC), Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2017-38 DC2017-44 |
This report proposes an optimal implementation of FFT circuit for mixed grained reconfigurable architecture using via-sw... [more] | VLD2017-38 DC2017-44 pp.67-72 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 11:20 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Implementation and Optimization of Parallel Prefix Adder Using Majority Function Daiki Matsumoto, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2017-46 DC2017-52 |
In recent FPGAs and post CMOS devices, three-input majority operation can be efficiently realized and circuit configuration... [more] | VLD2017-46 DC2017-52 pp.109-114 |
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2017-07-26 14:00 |
Akita | Akita Atorion-Building (Akita) | A Study on Implementation Method of Byzantine Fault Tolerant Systems Takeru Nanao, Yudai Ishikawa, Masashi Imai (Hirosaki Univ.) DC2017-17 |
A fault tolerant system does not cause a failure even if a fault occurs. The algorithm OM has been proposed as a basic B... [more] | DC2017-17 pp.7-12 |
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