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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-30 09:55 |
Kumamoto | (Primary: On-site, Secondary: Online) |
Design of Digital Phase-Locked Loop Circuit based on 3rd-Order MASH ΔΣ FDC for Low In-Band Phase Noise Ryoga Iwashita, Zule Xu, Masaru Osada, Ryoya Shibata, Yo Kumano, Tetsuya Iizuka (UTokyo)  VLD2022-43 ICD2022-60 DC2022-59 RECONF2022-66 |
$DeltaSigma$ frequency-to-digital converter based phase locked loops (FDC-PLLs) can reduce its quantization noise at low... [more] | VLD2022-43 ICD2022-60 DC2022-59 RECONF2022-66 pp.138-143 |
| CAS, CS | 2022-03-03 12:45 |
Online | Online | [Memorial Lecture]
Integration Techniques of Phase Locked Loops on high-speed and high- precision for wireline and wireless applications Masaru Kokubo (Hitachi) CAS2021-78 CS2021-80 |
The configurations of the PLLs for modulation are described. This paper summarizes the technical points in the integrate... [more] | CAS2021-78 CS2021-80 pp.25-30 |
| RISING (3rd) |
2021-11-17 11:00 |
Tokyo | (Primary: On-site, Secondary: Online) |
Study on Synchronization Strategy for Maximizing Received Power in Distributed Microwave Wireless Power Transfer Systems Kentaro Matsuura, Koeru Shin, Daisuke Kobuchi, Yoshiaki Narusue, Hiroyuki Morikawa (UTokyo) |
We propose a design strategy of the synchronization period to maximize the time-averaged received power in the distribut... [more] | |
| MW, ICD | 2019-03-15 11:00 |
Okinawa | An Energy-Saving Digital-to-Time Converter for Ultra-Low-Power Digital PLLs Hongye Huang, Hanli Liu, Zheng Sun, Teruki Someya, Atsushi Shirane, Kenichi Okada (Tokyo Tech) MW2018-172 ICD2018-116 |
A digital-to-time converter (DTC) could be a critical part in a digital phase-locked loop (PLL). Comparing to other DTC ... [more] | MW2018-172 ICD2018-116 pp.87-91 |
|
| ICD, CPSY, CAS | 2018-12-23 09:30 |
Okinawa | [Poster Presentation]
Evaluation of performance of 5GHz PLL with high-frequency injection pulses Yuuki Kojima, Takao Kihara, Tsutomu Yoshimura (OIT) CAS2018-97 ICD2018-81 CPSY2018-63 |
Recent years, The high-frequency and the low-jitter clock generation is required due to speeding up of the communication... [more] | CAS2018-97 ICD2018-81 CPSY2018-63 pp.81-82 |
|
| ICD, CPSY, CAS | 2018-12-23 09:30 |
Okinawa | [Poster Presentation]
Evaluation of jitter performance with external- and self-injection in PLL circuit Tatsuya Okafuji, Kazuki Miyao, Takao Kihara, Tsutomu Yoshimura (OIT) CAS2018-100 ICD2018-84 CPSY2018-66 |
In recent years, high-speed clock with high precision is required as communication speed increases. We have confirmed th... [more] | CAS2018-100 ICD2018-84 CPSY2018-66 pp.91-93 |
|
| MW | 2018-11-15 13:30 |
Nagasaki | Fukue Cultural Hall | Phase Control Method for Subsampling PLL by Varying Phase and Frequency of Clock Signal of S/H Circuit Osamu Wada, Hiroyuki Mizutani, Kenichi Tajima (Mitsubishi Electric Corp.) MW2018-97 |
A phase control method of PLL that generates a LO signal was reported as controlling a phase difference between transmi... [more] | MW2018-97 pp.31-34 |
| MW, ICD | 2017-03-03 10:25 |
Okayama | Okayama Prefectural Univ. | Study of Wide band width LC type Injection-locked Frequency Divider with Capacitor Array Yoshitake Nishino, Nobuyuki Itoh, Takayuki Morishita, Kiyotaka Komoku (Okayama Prefectural Univ.) MW2016-206 ICD2016-136 |
An injection-locked frequency divider（ILFD）with capacitor array is studied to obtain a wide locking range and high input... [more] | MW2016-206 ICD2016-136 pp.101-106 |
| OFT, OCS, IEE-CMN, ITE-BCT [detail] | 2016-11-10 16:25 |
Nagasaki | Nagasaki Shoko Kaigi Sho | Automatic pull-in operation in heterodyne phase-lock and homodyne detection of QPSK signals by microcomputer-assisted loop filter Yudai Hisata, Akira Mizutori, Masafumi Koga (Oita Univ.) OCS2016-58 |
This paper demonstrates signal light carrier automatic pull-in and phase-lock operation to optical frequency comb refere... [more] | OCS2016-58 pp.9-12 |
| EMCJ, IEE-EMC, IEE-MAG | 2015-06-25 10:10 |
Overseas | KMITL, Thailand | EMI Reduction by Extended Spread Spectrum in Switching Converter Yasunori Kobori (NIT, Oyama College/Gunma Univ.), Nobukazu Tsukiji, Nobukazu Takai, Haruo Kobayashi (Gunma Univ.) EMCJ2015-18 |
This paper proposes new EMI reduction method by extended spread spectrum using the PLL circuit with pseudo analog noise ... [more] | EMCJ2015-18 pp.1-6 |
| VLD | 2015-03-04 09:15 |
Okinawa | Okinawa Seinen Kaikan | On PLL Layouts Evaluation based on Transistor-array Style Yuki Miura, Atsushi Nanri, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2014-175 |
The transistor array(TA)-style is a layout methodology where an analog layout is configured on the pattern such that uni... [more] | VLD2014-175 pp.123-128 |
| NC | 2015-01-30 10:25 |
Fukuoka | Kyushu Institute of Technology | Winner-Take-All neural network with DPLL considering scalability Masaki Azuma, Hiroomi Hikawa (Kansai Univ.) NC2014-65 |
This paper proposes a hardware winner-take-all neural network (WTANN) that employs a new winner-take-all (WTA) circuit w... [more] | NC2014-65 pp.47-52 |
| PN, NS, OCS (Joint) |
2014-06-26 10:50 |
Oita | B-ConPlaza | Costas Loop Homodyne detection for 20Gbit/s QPSK signal transmission Yusuke Shigeta, Akira Mizutori, Masafumi Koga (Oita Univ.) OCS2014-12 |
The optical fiber transmission experiment confirmed a stable Costas-Loop homodyne detection for 20Gbit/s QPSK signal. Su... [more] | OCS2014-12 pp.1-4 |
| MW | 2014-03-05 16:15 |
Ehime | Ehime University | Novel phase difference control technique of fractional-N PLL by using clock-shift of LE signal Yusuke Kitsukawa, Hideyuki Nakamizo, Kazunari Kihira, Kenichi Tajima, Kenji Kawakami (Mitsubishi Electric) MW2013-223 |
A novel phase control technique of microwave signals using a Fractional-N PLL(F-PLL) synthesizer is described. In multip... [more] | MW2013-223 pp.151-154 |
| ICD | 2014-01-28 15:00 |
Kyoto | Kyoto Univ. Tokeidai Kinenkan | [Poster Presentation]
An ultra-low-voltage power-supply monitor circuit for wireless-powered microparticle manipulation system Ji Cui, Hirosuke Iwasaki, Yoshiaki Dei, Toshimasa Matsuoka (Osaka Univ.) ICD2013-105 |
This paper presents a voltage sensor (VS) circuit to monitor the supply voltage induced on wireless-pow-ered micropartic... [more] | ICD2013-105 pp.15-18 |
| ICD | 2014-01-28 15:00 |
Kyoto | Kyoto Univ. Tokeidai Kinenkan | [Poster Presentation]
A Design of 0.5V Subthreshold Digital Phase Locked Loop using Simple Synchronization Unit. Kousuke Watanabe, Tomochika Harada (Yamagata Univ.) ICD2013-129 |
In this paper, we design and evaluate the 0.5V subthreshold DPLL circuit. Under synchronization, fine tuning operation i... [more] | ICD2013-129 pp.67-72 |
| DC | 2013-12-13 13:25 |
Ishikawa | Variable Test-Timing Generation for Built-In Self-Test on FPGA Yasuo Sato, Munehiro Matsuura, Hitoshi Arakawa, Yousuke Miyake, Seiji Kajihara (Kyushu Inst. of Tech.) DC2013-69 |
This paper proposes a variable test-timing generation method that should be used for built-in self-test on FPGA. Applica... [more] | DC2013-69 pp.7-12 |
|
| ICD | 2012-12-17 15:55 |
Tokyo | Tokyo Tech Front | [Poster Presentation]
A New Approach of the Analysis of the ISF in Oscillators with a Closed-Loop Control Junki Mizuno, Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino (OIT), Yoshio Matsuda (Kanazawa Univ.) ICD2012-97 |
The derivation of the impulse sensitivity function (ISF) of oscillators are widely used for the evaluation of the phase ... [more] | ICD2012-97 pp.37-40 |
| ICD | 2012-12-17 15:55 |
Tokyo | Tokyo Tech Front | [Poster Presentation]
Analysis of the Pull-in Range in a CDR-PLL with the Nonlinearity of the Phase Detector Shinji Shimizu, Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino (OIT), Yoshio Matsuda (Kanazawa Univ.) ICD2012-100 |
The analysis of the lock-in process of CDR-PLLs using the nonlinear model of the phase detector is presented. The analys... [more] | ICD2012-100 pp.45-48 |
| EMCJ, ITE-BCT | 2012-03-16 14:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Study on Phase Comparator Sesitivity for Low Phase-Noise PLL Hideyasu Hobara, Yoshiki Kayano, Hiroshi Inoue (Akita Univ.) EMCJ2011-141 |
An UWB RF system can be used in the area of signal processing. The phase-noise of output voltage of the oscillator with ... [more] | EMCJ2011-141 pp.67-72 |
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