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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2015-12-02
15:00		 Nagasaki Nagasaki Kinro Fukushi Kaikan Problems that occur in FPGAs communication -- Cautionary point of PCIe Gen3 --
Hirotaka Takayama, Yoshiki Yamaguchi (Tsukuba Univ.) RECONF2015-54		 The purpose of this study investigates of suppressed bandwidth problem of PCI-Express. This problem makes communication ... [more] RECONF2015-54
pp.33-38
RECONF 2011-09-27
09:25		 Aichi Nagoya Univ. A Design Framework for relieving a HW Bottleneck FPGAs Connected with a High-Speed Data Bus
Koichi Araki, Yukinori Sato, Yasushi Inoguchi (JAIST) RECONF2011-33		 As reconfigurable devices with a PCI-Express interface appear in the market, the data transfer speed between the reconfi... [more] RECONF2011-33
pp.63-68
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2010-12-01
10:45		 Fukuoka Kyushu University An Effective Processing Method for Parallel Loops on FPGA with PCI-Express
Koichi Araki, Yukinori Sato, Yasushi Inoguchi (JAIST) RECONF2010-47		 As FPGAs with a PCI-Express Interface appear in the market, the data transter speed between FPGA and other units, such a... [more] RECONF2010-47
pp.49-54
NS, IN
(Joint)		 2007-03-09
16:20		 Okinawa Okinawa Convention Center A Congestion Control Algorithm for Low-Latency Ethernet LAN Communications
Hideyuki Shimonishi, Junichi Higuchi, Takashi Yoshikawa, Atsushi Iwata (NEC) NS2006-244		 Ethernet is seeking for its new applications to CPU-CPU and CPU-I/O communications used in, for example, a PCI-Express e... [more] NS2006-244
pp.453-458
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