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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF | 2012-05-29 17:35 |
Okinawa | Tiruru (Naha Okinawa, Japan) | Development of Application for Heterogeneous Multi-Core Processor Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano (Keio Univ.), Ryuichi Sakamoto, Mitaro Namiki (Tkyo Univ. of Agri. and Tech.)  RECONF2012-16 |
This paper describes the application development on a heterogeneous multi-core processor that consists of a CPU and acce... [more] | RECONF2012-16 pp.89-94 |
| CPSY | 2011-10-21 11:00 |
Hyogo | Design of a Method for Coexistence of 32/64-bit Kernels Daiki Nakahara, Yoshinari Nomura, Hideo Taniguchi (Okayama Univ.) CPSY2011-29 |
As wide spreading of 64-bit CPUs, Operating System (OS) is changing its architecture-base from 32-bit to 64-bit. Softwar... [more] | CPSY2011-29 pp.25-30 |
|
| DC, CPSY (Joint) |
2011-07-29 09:25 |
Kagoshima | 3-D Stacked Architecture using Inductinve Coupling Eiichi Sasaki, Daisuke Sasaki, Hiroki Matsutani, Hideharu Amano, Yasuhiro Take, Tadahiro Kuroda (Keio Univ.), Ryuichi Sakamoto, Mitaro Namiki (TAT) CPSY2011-10 |
Cube-1: a low power heterogeneus 3-D stacked architecture using an inductive-coupling is proposed. A low power MIPS R3... [more] |
CPSY2011-10 pp.7-12 |
|
| ICD, IPSJ-ARC | 2011-01-21 11:40 |
Kanagawa | Keio University (Hiyoshi Campus) | Acceleration of Block Matching by using Multiple Alignments on Heterogeneous Multi-Core Processor Yoshitaka Hiramatsu (Hitachi), Hasitha Muthumala Waidyasooriya, Masanori Hariyama (Tohoku Univ.), Tohru Nojiri, Kunio Uchiyama (Hitachi) |
The large data-transfer time among different cores and data-supply time to arithmetic unit is a big problem in heterogen... [more] | ICD2010-136 pp.57-62 |
| VLD | 2010-09-27 14:25 |
Kyoto | Kyoto Institute of Technology | Accelerator-Centric Task Allocation Based on Algorithm Transformation for Heterogeneous Multicore Processors Masanori Hariyama, Hasitha Muthumala Waidyasooriya, Michitaka Kameyama (Tohoku Univ.) VLD2010-43 |
Heterogeneous multi-core processors are attracted by the media processing applications due to their capability of drawi... [more] |
VLD2010-43 pp.7-12 |
| RECONF | 2010-09-16 11:00 |
Shizuoka | Shizuoka University (Faculty of Eng., Hall 2) | Development of an On-chip Pattern Recognition System using Dynamic and Partial Reconfiguration Hiroyuki Kawai, Moritoshi Yasunaga (Tsukuba Univ.) RECONF2010-18 |
In this paper, we develop an on-chip pattern recognition system. The feature of this system is that two Microblaze core... [more] |
RECONF2010-18 pp.1-6 |
| CPSY, DC (Joint) |
2010-08-03 - 2010-08-05 |
Ishikawa | Kanazawa Cultural Hall | A Consideration of Speculative Memory Access in Two-Path Limited Speculation System Hiroyoshi Jutori, Akihiro Fukuda, Tsubasa Tsuda, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2010-18 |
We have proposed two-path limited speculation method and a multi-core processor architecture PALS which based on the met... [more] | CPSY2010-18 pp.61-66 |
| CPSY, DC (Joint) |
2009-08-04 - 2009-08-05 |
Miyagi | Pipelined Multithreading with Clustered Communication on Commodity Multi-Core Processors *Yuanming Zhang, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2009-26 |
Recently proposed pipelined multithreading (PMT) techniques have shown great applicability to parallelizing general prog... [more] | CPSY2009-26 pp.97-102 |
|
| NLP | 2009-05-15 13:55 |
Shiga | Ritsumeikan University | Estimation of Parallel Computing for ADI-FDTD Method with Relaxation Method Naoki Oguni, Hideki Asai (Shizuoka Univ) NLP2009-6 |
In this paper, we present the parallel ADI-FDTD method for electromagnetic simulation. FDTD and ADI-FDTD method have bee... [more] | NLP2009-6 pp.25-30 |
| SR, RCS, USN, AN (Joint) |
2008-10-24 11:35 |
Okinawa | Okinawa industry support center | Preliminary Analysis of Low Power Multi-Core CPU for Wireless Sensor Node Sotaro Ohara, Makoto Suzuki, Shunsuke Saruwatari, Masateru Minami, Hiroyuki Morikawa (The University of Tokyo) USN2008-59 |
For wireless nensor nodes, it is important to reduse power consumption while completing tasks within their deadline. We ... [more] | USN2008-59 pp.123-128 |
| CS, IN, NS (Joint) |
2008-09-12 13:00 |
Miyagi | Tohoku University | A study of high performance data transfer by software-based parallel TCP/IP stack Masato Yasuda, Kiyohisa Ichino, Hiroshi Ueno (NEC) NS2008-59 |
In recent years, network traffic on the internet is growing and there is a demand of high-performance network processing... [more] | NS2008-59 pp.99-104 |
| ICD, SDM | 2007-08-23 08:30 |
Hokkaido | Kitami Institute of Technology | Development of a Multi-Core SoC with 9 CPUs and 2 Matrix Processors Masami Nakajima, Koichi Ishimi, Hayato Fujiwara, Kazuya Ishida, Naoto Okumura, Norio Masui, Hiroyuki Kondo (Renesas) SDM2007-141 ICD2007-69 |
A multi-core SoC for multi-application (recognition, inference, measurement, control, and security) is developed. The co... [more] | SDM2007-141 ICD2007-69 pp.1-4 |
| ICD, SDM | 2007-08-23 09:20 |
Hokkaido | Kitami Institute of Technology | Evaluation of Heterogeneous Multicore Architecture with AAC-LC Stereo Encoding Hiroaki Shikano (Hitachi/./Waseda Univ.), Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Masafumi Onouchi, Kunio Uchiyama (Hitachi), Toshihiko Odaka (Hitachi/./Waseda Univ.), Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta (Renesas Technology), Yasutaka Wada, Keiji Kimura, Hironori Kasahara (Waseda Univ.) SDM2007-143 ICD2007-71 |
This paper describes a heterogeneous multi-core processor (HMCP) architecture which integrates general purpose processor... [more] | SDM2007-143 ICD2007-71 pp.11-16 |
| AI | 2007-05-31 10:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Parallel SAT Solver for Multi-Core Processor Environment Akihide Takami, Koji Iwanuma, Hidetomo Nabeshima (Univ. of Yamanashi) AI2007-2 |
In this paper, we propose a new parallel SAT solver based on the fastest sequential SAT solver ”Mini- Sat” for a multi-... [more] |
AI2007-2 pp.7-12 |
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