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Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM, ICD, ITE-IST [detail] 2021-08-18
Online Online Performance Evaluation of Serial-Parallel Montgomery Multipliers for RNS
Hiroyuki Tsubouchi, Mitsunaga Kinjo, Katsuhiko Shimabukuro (Univ. of the Ryukyus) SDM2021-40 ICD2021-11
Modulo operations are required in RNS (Residue Number System) which enables to perform highly parallel computation. Also... [more] SDM2021-40 ICD2021-11
HWS, ICD [detail] 2019-11-01
Osaka DNP Namba SS Bld. A Design of Isogeny-Based Cryptographic Hardware Architecture Using Residue Number System
Shuto Funakoshi, Rei Ueno, Naofumi Homma (Tohoku Univ.) HWS2019-60 ICD2019-21
In this paper, we will propose an efficient hardware architecture of isogeny-based cryptography. The proposed architectu... [more] HWS2019-60 ICD2019-21
ISEC, SITE, ICSS, EMM, HWS, BioX, IPSJ-CSEC, IPSJ-SPT [detail] 2019-07-24
Kochi Kochi University of Technology Design Space Search Applying Bayesian Optimization to High-level Design Flow
Ryohei Nakayama (UTokyo), Hiromitsu Awano (Osaka Univ.), Makoto Ikeda (UTokyo) ISEC2019-57 SITE2019-51 BioX2019-49 HWS2019-52 ICSS2019-55 EMM2019-60
Now that circuit scale is increasing, high-level synthesis technology that designs circuits using high-level programming... [more] ISEC2019-57 SITE2019-51 BioX2019-49 HWS2019-52 ICSS2019-55 EMM2019-60
HWS, ICD 2018-10-29
Osaka Kobe Univ. Umeda Intelligent Laboratory Selection and evaluation of optimal bases in the case of implementing Q-RNS MR algorithm in FPGA
Yoshihiro Kori, Daisuke Fujimoto, Yu-ichi Hayasi (NAIST), Naofumi Homma (Tohoku Univ.) HWS2018-51 ICD2018-43
To improve a computation speed of public cryptography, Montgomery Reduction(MR) and Residue Number System (RNS) are ofte... [more] HWS2018-51 ICD2018-43
HWS 2018-04-13
Fukuoka   Energy Evaluation of FPGA Pairing Implementation with Pipeline Modular Multiplier
Yusuke Nagahama, Daisuke Fujimoto, Junichi Sakamoto, Tsutomu Matsumoto (YNU) HWS2018-5
Energy consumption and latency are important features of dedicated hardware bilinear pairing calculators. However publi... [more] HWS2018-5
IT, ISEC, WBS 2016-03-10
Tokyo The University of Electro-Communications A Multiplier Architecture for Finite Field of 254bit-Prime Square Order Based on Pipelined 32bit Montgomery Multipliers
Yusuke Nagahama, Daisuke Fujimoto, Tsutomu Matsumoto (YNU) IT2015-116 ISEC2015-75 WBS2015-99
Bilinear Pairing is a major tool to realize advanced cryptographic functionality such as searchable encryption, aggregat... [more] IT2015-116 ISEC2015-75 WBS2015-99
(Joint) [detail]
Nagasaki Nagasaki Kinro Fukushi Kaikan Implementation of ECDSA Using Gate-level Pipelined Self-synchronous Circuit
Masato Tamura, Makoto Ikeda (Univ. of Tokyo) VLD2015-39 DC2015-35
In this paper, we investigated the implementation method of elliptic curve digital signature algorithm using self-synchr... [more] VLD2015-39 DC2015-35
CPSY 2014-11-14
Hiroshima Hiroshima University C2CU : A CUDA C Program Generator for Bulk Execution of a Sequential Algorithm
Daisuke Takafuji, Koji Nakano, Yasuaki Ito (Hiroshima Univ.) CPSY2014-67
A sequential algorithm is oblivious if an address accessed at each time does not depend on input data. Many important ta... [more] CPSY2014-67
ISEC 2011-05-13
Tokyo Kikai-Shinko-Kaikan Bldg. A Study on Side Channel Cryptanalysis of RSA Hardware Focused on Operands for Multiple-precision Multiplication
Takeshi Kishikawa, Tsutomu Matsumoto (YNU) ISEC2011-8
A lot of side channel attack methods and countermeasures have been studied for modular powering based cryptosystems such... [more] ISEC2011-8
IT, ISEC, WBS 2010-03-04
Nagano Nagano-Engineering Campus, Shinshu University An RSA Encryption Hardware Algorithm that uses a DSP block on the FPGA
Kensuke Kawakami, Koji Nakano (Hiroshima Univ.) IT2009-80 ISEC2009-88 WBS2009-59
The main contribution of this paper is to present an efficient hardware algorithm for modular exponentiation, which is a... [more] IT2009-80 ISEC2009-88 WBS2009-59
CAS, SIP, VLD 2007-06-22
Hokkaido Hokkaido Tokai Univ. (Sapporo) Scalable Dual-Radix Unified Montgomery Multiplier in GF(p) and GF(2n)
Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) CAS2007-26 VLD2007-42 SIP2007-56
Modular multiplication is the dominant arithmetic operation in elliptic curve cryptography (ECC), which is one of public... [more] CAS2007-26 VLD2007-42 SIP2007-56
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