| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF | 2012-05-29 17:35 |
Okinawa | Tiruru (Naha Okinawa, Japan) | Development of Application for Heterogeneous Multi-Core Processor Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano (Keio Univ.), Ryuichi Sakamoto, Mitaro Namiki (Tkyo Univ. of Agri. and Tech.)  RECONF2012-16 |
This paper describes the application development on a heterogeneous multi-core processor that consists of a CPU and acce... [more] | RECONF2012-16 pp.89-94 |
| ICD, IPSJ-ARC, IPSJ-EMB | 2009-01-13 10:30 |
Osaka | Shoushin Kaikan | [Invited Talk]
Evolution of application processor OMAP for mobile products Masahiro Miyazaki (Texas Inst. Japan Limited) ICD2008-131 |
Abstract This presentation shows the evolution of application processor OMAP. Recently, high performance multimedia and ... [more] | ICD2008-131 pp.13-17 |
| ICD, IPSJ-ARC | 2008-05-14 09:00 |
Tokyo | A Scalable Multi-core Processor for Mobile Multimedia Applications Hiroyuki Usui, Shuou Nomura, Fumiyuki Yamane, Yukimasa Miyamoto, Chaiyasit Kumtornkittikul, Jun Tanabe, Masato Uchiyama, Takashi Miyamori, Yoshiro Tsuboi (Toshiba) ICD2008-25 |
We implemented multi-core processor for mobile multimedia applications. Each core consists of 32bit RISC processor and t... [more] | ICD2008-25 pp.39-44 |
|
| VLD, ICD | 2008-03-07 09:40 |
Okinawa | TiRuRu | Enhancing Multimedia Processing by Wave-Pipelining a Multifunctional Execution Unit Kazunori Noda, Atuko Yokoyama, Hiroki Takeda, Masa-aki Fukase, Tomoaki Sato (Hirosaki Univ.) VLD2007-157 ICD2007-180 |
A multimedia mobile processor HCgorilla developed for ubiquitous network was built in Java CPU, cipher logic, and floati... [more] | VLD2007-157 ICD2007-180 pp.7-12 |
| CPSY | 2007-10-25 15:50 |
Kumamoto | Kumamoto University | Acceleration of AES Encryption with CAM-Enhanced Massive-Parallel SIMD Matrix Processor Masakatsu Ishizaki, Takeshi Kumaki, Masaharu Tagami, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.), Takayuki Gyohten, Hideyuki Noda, Yoshihiro Okuno, Kazutami Arimoto (Renesas Technology) CPSY2007-28 |
We have previously reported that the Content Addressable Memory (CAM)-enhanced massive-parallel Single Instruction Multi... [more] | CPSY2007-28 pp.25-30 |
| ICD, SIP, IE, IPSJ-SLDM | 2006-10-26 11:30 |
Miyagi | Super parallel SIMD processor with CAM based high-speed pattern matching capability Yutaka Kono, Takeshi Kumaki, Masakatsu Ishizaki, Masaharu Tagami, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.), Takayuki Gyohten, Hideyuki Noda, Yasuto Kuroda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito (Renesas) |
A super parallel SIMD processor has been developed for handling the increasing amount of multimedia data efficiently. ... [more] |
SIP2006-90 ICD2006-116 IE2006-68 pp.39-44 |
|
| ICD | 2006-05-25 13:00 |
Hyogo | Kobe University | A 40GOPS 250mW Massively Parallel Processor Based on Matrix Architecture
-- A Very High Performance Processor IP for Mobile System-on-Chips -- Kiyoshi Nakata, Masami Nakajima, Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten (Renesas) |
We have developed a massively parallel processor based on Matrix architecture. This architecture achieved 40GOPS of 16-b... [more] | ICD2006-25 pp.19-23 |
| ICD | 2006-05-25 14:45 |
Hyogo | Kobe University | [Special Invited Talk]
Technological trend of advanced processsors pursuing high performance/watt Kunio Uchiyama (Hitachi) |
Recently, power consumption is the most critical theme in developing various kinds of processors. Although increasing th... [more] | ICD2006-28 pp.37-42 |
| SIP, ICD, IE, IPSJ-SLDM | 2005-10-21 13:00 |
Miyagi | Ichinobo, Sakunami-Spa | [Invited Talk]
Technology for Embedded Processors Kunio Uchiyama (Hitachi) |
Embedded processors which are used in recent digital consumer appliances must satisfy the requirements of high-performan... [more] | SIP2005-122 ICD2005-141 IE2005-86 pp.43-47 |
| CAS, SIP, VLD | 2005-06-27 14:55 |
Miyagi | Tohoku University | A Hardware Oriented Design for Weighted Median Filters. (口頭発表) Anitha govindarajan (Post graduate student) |
Median and rank order filters are very important types of filters in image processing well known for their ability in re... [more] | |
| IE, SIP, ICD, IPSJ-SLDM | 2004-10-21 15:25 |
Yamagata | Noise and process variation-tolerant multi-ported register file using 130 nm technology Yuuichirou Ikeda, Masaya Sumita (Matsushita Electric Industrial) |
We have developed a 32-bit, 64-word 9-read, 7-write ported register file for a processor based on 130 nm process technol... [more] | SIP2004-87 ICD2004-119 IE2004-63 pp.67-72 |
|
| IE, SIP, ICD, IPSJ-SLDM | 2004-10-22 09:20 |
Yamagata | 3D Graphics Processor for Mobile Set based on Configurable Processor Takashi Takemoto, Yasuharu Takenaka, Tsutomu Minagawa, Tomohiro Koizumi, Yasuyuki Ushijima, Naoaki Yanagida, Yasuo Ohara, Kouichi Tanaka, Yasuhiko Fujita (Toshiba Corp.) |
A media processor named T4G is described. T4G integrates 3.5M polygon/sec 3D Graphic engine, 15fps@QVGA MPEG4 engine, 2M... [more] | SIP2004-89 ICD2004-121 IE2004-65 pp.1-6 |
|
| IE, SIP, ICD, IPSJ-SLDM | 2004-10-22 10:50 |
Yamagata | A DSP Engine for an Extensible Media Embedded Processor Toshiyuki Furusawa (Toshiba Microelectronics), Satoshi Inoue, Isao Katayama, Yoshihisa Arai, Masataka Matsui, Meisei Nishikawa, Takeshi Yoshimoto (Toshiba) |
An extension interface for a configurable processor enabling implementation of an application specific programmable DSP ... [more] | SIP2004-92 ICD2004-124 IE2004-68 pp.19-24 |
|
[Return to Top Page]