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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 11:20 |
Miyazaki |
NewWelCity Miyazaki |
Power-Gating Circuit Scheme for Transient-Glitch Energy Reduction Yuya Ohta, Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2011-90 DC2011-66 |
In fine-grain power gating which performs cell-by-cell power gating (PG) , energy overhead consumed at sleep-in and slee... [more] |
VLD2011-90 DC2011-66 pp.221-226 |
VLD, CAS, SIP |
2008-06-26 14:45 |
Hokkaido |
Hokkaido Univ. |
A study for performance modeling of circuits using MTCMOS power gating Yusuke Hikosaka, Yuichiro Tachikawa, Junki Miyajima, Masahiro Fukui (Ritsumeikan Univ.) CAS2008-13 VLD2008-26 SIP2008-47 |
In the processes before the 90 nm generation, most of the power is consumed by the dynamic power which is consumed by th... [more] |
CAS2008-13 VLD2008-26 SIP2008-47 pp.69-74 |
VLD, IPSJ-SLDM |
2008-05-09 13:30 |
Hyogo |
Kobe Univ. |
Fine-Grained Power Gating Based on the Controlling Value of Logic Gates Lei Chen (Waseda Univ.), Takashi Horiyama (Saitama Univ.), Yuichi Nakamura (NEC), Shinji Kimura (Waseda Univ.) VLD2008-10 |
Leakage power dissipation of logic gates has become an increasingly important problem. A novel fine-grained power gating... [more] |
VLD2008-10 pp.19-24 |
VLD, ICD |
2008-03-06 10:05 |
Okinawa |
TiRuRu |
Design and Analysis of on-chip leakage monitor using MTCMOS Satoshi Koyama, Seidai Takeda, Kimiyoshi Usami (S.I.T.) VLD2007-146 ICD2007-169 |
On cutting-edge semiconductor process, leakage current varies drastically due to process variation and temperature chang... [more] |
VLD2007-146 ICD2007-169 pp.13-18 |
RECONF, CPSY, VLD, IPSJ-SLDM |
2008-01-16 15:10 |
Kanagawa |
Hiyoshi Campus, Keio University |
Development of verification and power estimation methodology for circuits with Run Time Power Gating Mitsutaka Nakata, Toshiaki Shirai, Toshihiro Kashima, Seidai Takeda, Kimiyoshi Usami (S.I.T.), Naomi Seki, Yohei Hasegawa, Hideharu Amano (Keio Univ.) VLD2007-111 CPSY2007-54 RECONF2007-57 |
When applying Run-Time Power Gating (RTPG) to a design,logic verification is one of the major problems.Gate-level simula... [more] |
VLD2007-111 CPSY2007-54 RECONF2007-57 pp.37-42 |
RECONF, CPSY, VLD, IPSJ-SLDM |
2008-01-16 15:35 |
Kanagawa |
Hiyoshi Campus, Keio University |
Physical design and Evaluation of MIPS R3000 processor applying Run Time Power Gating Toshiaki Shirai, Toshihiro Kashima, Seidai Takeda, Mitsutaka Nakata, Kimiyoshi Usami (S.I.T.), Yohei Hasegawa, Naomi Seki, Hideharu Amano (Keio Univ.) VLD2007-112 CPSY2007-55 RECONF2007-58 |
Run Time Power Gating (RTPG) is a technology that reduces leakage power in a temporally/spatially fine-grained manner. T... [more] |
VLD2007-112 CPSY2007-55 RECONF2007-58 pp.43-48 |
ICD, SDM |
2005-08-18 14:30 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
Delay Modeling and Static Timing Analysis for MTCMOS Circuits Naoaki Ohkubo, Kimiyoshi Usami (Shibaura Institute of Tech.) |
One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a dela... [more] |
SDM2005-138 ICD2005-77 pp.61-66 |
EE |
2005-07-22 15:40 |
Kyoto |
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Sub-1V Power Supply System with Variable-stage SC-type DC-DC Converter Scheme for Ambient Energy Sources Yoshihumi Yoshida, Humiyasu Utsunomiya (Seiko Instruments), Takakuni Douseki (NTT) |
This paper describes a sub-1-V power-supply, which is useful for self-powered short-range wireless systems with ambient ... [more] |
EE2005-30 pp.103-108 |
ICD |
2004-12-17 11:30 |
Hiroshima |
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The Power Reduction of Execution Circuits with Dynamic Power Control Method Sinji Itano, Keikiti Tamaru (OUS) |
The increase of leakage current in the deep submicron MOSFET circuits becomes the serious problems. In this paper the lo... [more] |
ICD2004-196 pp.19-24 |
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