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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
MI 2024-03-04
10:10		 Okinawa OKINAWAKEN SEINENKAIKAN
(Primary: On-site, Secondary: Online)		 Segmentation of lung nodules in CT using an ensemble of multiple MTANN
Kentaro Someya, Shogo Kodera, Hiroko Oshibe, Jin Ze, Kenji Suzuki (Tokyo Tech) MI2023-67		 It is challenging to accurately and robustly segment ground-glass opacity (GGO) nodules. In this study, we propose an ac... [more] MI2023-67
pp.113-116
RCS 2013-10-17
11:00		 Tokyo Sophia Univ. A Study on Downlinik/Uplink Power Control Technique for Dynamic TDD based Small Cell Systems
Hiroki Takahashi, Kazunari Yokomakura, Kimihiko Imamura (Sharp) RCS2013-146		 This paper proposes a downlink (DL)/uplink (UL) transmission power control (TPC) scheme for dynamic time division duplex... [more] RCS2013-146
pp.25-30
IA 2012-10-18
16:30		 Overseas Phuket A lightweight method to discriminate spamming hosts by periodically changing DNS response
Naoya Kitagawa, Hiroki Takakura (Nagoya Univ.), Tsunehiko Suzuki (Chukyo Univ.) IA2012-39		 With widespread of IPv6 usage, current anti-spam techniques which depend on reputations of IP address are losing their a... [more] IA2012-39
pp.31-35
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]		 2007-11-22
15:45		 Fukuoka Kitakyushu International Conference Center Memory Assignment Method Considering Orders of Operands for Massively Parallel Fine-grained SIMD Processor
Akira Kobashi, Ittetsu Taniguchi, Hiroaki Tanaka, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.), Kiyoshi Nakata (Renesas) VLD2007-104 DC2007-59		 In recent years, spread of data intensive multimedia applications equires high-performance in embedded systems.
Massiv... [more]		 VLD2007-104 DC2007-59
pp.91-96
VLD, IPSJ-SLDM 2007-05-10
13:30		 Kyoto Kyodai Kaikan Memory Assignment Method for Matrix Processing Array
Akira Kobashi, Ittetsu Taniguchi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.), Kiyoshi Nakata (Renesas) VLD2007-1		 MTA (MaTrix processing Array), which is developed by Renesas Technology Corp., can achieve high performance for digital ... [more] VLD2007-1
pp.1-6
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