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Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF 2011-09-27
09:00		 Aichi Nagoya Univ. Case Studies on an FPGA with System-Level Multiprocessor Design Toolset
Seiya Shibata, Yuki Ando, Shinya Honda (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.) RECONF2011-32		 This paper presents a system-level multiprocessor design toolkit: SystemBuilder. SystemBuilder enables system designers... [more] RECONF2011-32
pp.57-62
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-30
12:20		 Kanagawa   A Multi-layer Bus Architecture Optimization Algorithm for MPSoC in Embedded Systems
Harunobu Yoshida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Masayoshi Tachibana (KUT) VLD2008-115 CPSY2008-77 RECONF2008-79		 In this paper, we propose an on-chip bus optimization algorithm for a multi-layer bus architecture. Our algorithm effici... [more] VLD2008-115 CPSY2008-77 RECONF2008-79
pp.141-146
ICD, IPSJ-ARC, IPSJ-EMB 2009-01-14
17:00		 Osaka Shoushin Kaikan An H.264/AVC High422 Profile and MPEG-2 422 Profile Encoder LSI for HDTV Broadcasting Infrastructures
Koyo Nitta (NTT), Mitsuo Ikeda (NEL), Hiroe Iwasaki, Takayuki Onishi, Takashi Sano, Atsushi Sagata, Yasuyuki Nakajima (NTT), Minoru Inamori (NEL), Takeshi Yoshitome (NTT), Hiroaki Matsuda (NEL), Ryuichi Tanida, Atsushi Shimizu, Ken Nakamura, Jiro Naganuma (NTT) 		An H.264/AVC encoder LSI (named “SARA/E”) that supports High422 profile, as well as 422 profile of MPEG-2, has been deve... [more] ICD2008-149
pp.117-122
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