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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM | 2023-06-26 10:10 |
Hiroshima | Hiroshima Univ. (Res. Inst. of Nanodevices) | [Memorial Lecture]
Optimum Design of Channel Material and Surface Orientation for Extremely Thin Body nMOSFETs Based on Nonlinear Modeling of Surface Roughness Scattering Kei Sumita, Min-Soo Kang, Chia-Tsong Chen, Kasidit Toprasertpong, Mitsuru Takenaka, Shinichi Takagi (U. Tokyo)  SDM2023-27 |
Nano-sheet channel has been recently adopted in logic CMOS as the next-generation channel for FinFET because the nano-sh... [more] | SDM2023-27 pp.1-4 |
| SDM | 2021-01-28 16:05 |
Online | Online | [Invited Talk]
Subband Engineering by Combination of Channel Thickness Scaling and (111) Surface Orientation in InAs-On-Insulator nMOSFETs Kei Sumita, Kasidit Toprasertpong, Mitsuru Takenaka, Shinich Takagi (Univ.of Tokyo) SDM2020-54 |
There has been three essential challenges of III-V nMOSFETs: (1) Low semiconductor capacitance, (2) Strong thickness flu... [more] | SDM2020-54 pp.21-24 |
| SDM | 2016-10-27 10:50 |
Miyagi | Niche, Tohoku Univ. | Behavior of Random Telegraph Noise toward Bias Voltage Changing Takezo Mawaki, Akinobu Teramoto, Rihito Kuroda, Shinya Ichino, Tetsuya Goto, Tomoyuki Suwa, Shigetoshi Sugawa (Tohoku Univ.) SDM2016-75 |
As the progression of MOSFETs scaling down continues, the impacts of RTN (Random Telegraph Noise) on the MOSFETs have be... [more] | SDM2016-75 pp.35-38 |
| RECONF, CPSY, VLD, IPSJ-SLDM [detail] | 2015-01-29 17:00 |
Kanagawa | Hiyoshi Campus, Keio University | Temperature sensor applying Body Bias in Silicon-on-Thin-BOX Tsubasa Kosaka, Shohei Nakamura, Kimiyoshi Usami (S.I.T.) VLD2014-127 CPSY2014-136 RECONF2014-60 |
The performance advancement by the transistor scaling is blocked by increase of power consumption and process variation.... [more] | VLD2014-127 CPSY2014-136 RECONF2014-60 pp.99-104 |
| SDM | 2013-11-14 15:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Advanced MOSFET simulations using a quantum energy trasport model Shohiro Sho, Shinji Odanaka (Osaka Univ.) SDM2013-105 |
A quantum energy transport(QET) model is derived by using a diffusion scaling in the quantum hydrodynamic (QHD) model. I... [more] | SDM2013-105 pp.31-36 |
| SDM | 2012-11-16 10:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg | Prospect of Low-Energy Operation of Scaled Cross-Current Tetrode (XCT) SOI CMOS Daiki Sato, Yasuhisa Omura (Kansai Univ.) SDM2012-105 |
This paper introduces an advanced performance of cross-current tetrode (XCT) SOI CMOS devices and demonstrates their out... [more] | SDM2012-105 pp.31-36 |
| SDM | 2010-11-12 15:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Design Feasibility of Si Wire GAA MOSFET
-- Analytical model for the design guideline -- Shunsuke Nakano, Yasuhisa Omura (Kansai Univ.) SDM2010-184 |
This paper proposes a simple model to examine the design feasibility of Si wire gate-all-around (GAA) metal-oxide-semico... [more] | SDM2010-184 pp.71-76 |
| ED, SDM | 2010-07-02 12:45 |
Tokyo | Tokyo Inst. of Tech. Ookayama Campus | Evaluation of 1/f Noise Characteristics in High-k/Metal Gate and SiON/Poly-Si Gate MOSFET Takuya Imamoto, Takeshi Sasaki, Tetsuo Endoh (Tohoku Univ.) ED2010-95 SDM2010-96 |
In this paper, we compare the 1/f noise characteristics of High-k/Metal Gate MOSFET and SiON/Poly-Si Gate MOSFET by meas... [more] | ED2010-95 SDM2010-96 pp.195-198 |
| ED, SDM | 2010-07-02 15:45 |
Tokyo | Tokyo Inst. of Tech. Ookayama Campus | Study on Impurity Distribution Dependence of Electron-Dynamics in Vertical MOSFET Masakazu Muraguchi, Tetsuo Endoh (Tohoku Univ./JST) ED2010-120 SDM2010-121 |
In this study, we focus on the electron propagation in the V-MOSFET under the different impurity distribution of the pil... [more] | ED2010-120 SDM2010-121 pp.309-313 |
| SDM | 2009-11-13 13:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Tutorial Invited Lecture]
Possible Performance of SOI Devices, their Potentiality and Prospects
-- Past Constraint and Current Issues -- Yasuhisa Omura (Kansai Univ.) SDM2009-146 |
This report summarizes the present stage of SOI MOSFET technology and the aim and prospect of 3-D scaled MOSFET technolo... [more] | SDM2009-146 pp.61-66 |
| ICD, SDM | 2009-07-16 15:50 |
Tokyo | Tokyo Institute of Technology | The Study of Mobility-Tinv Trade-off in Deeply Scaled High-k/Metal Gate Devices and Scaling Design Guideline for 22nm-node Generation Masakazu Goto, Shigeru Kawanaka, Seiji Inumiya, Naoki Kusunoki, Masumi Saitoh, Kosuke Tatsumura, Atsuhiro Kinoshita, Satoshi Inaba, Yoshiaki Toyoshima (Toshiba) SDM2009-107 ICD2009-23 |
The trade-off between Tinv scaling and carrier mobility () degradation in deeply scaled HK/MG nMOSFETs has been ... [more] | SDM2009-107 ICD2009-23 pp.53-56 |
| ICD, SDM | 2008-07-17 14:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Special Talk]
Present Status and Future Trend of Characteristic Variations in Scaled CMOS Toshiro Hiramoto (Univ. of Tokyo/MIRAI-Selete), Kiyoshi Takeuchi, Takaaki Tsunomura (/MIRAI-Selete), Arifin T.Putra (Univ. of Tokyo), Akio Nishida, Shiro Kamohara (/MIRAI-Selete) SDM2008-135 ICD2008-45 |
The variability is one of the most critical issues for further miniaturization of MOS transistors. Although the variabi... [more] | SDM2008-135 ICD2008-45 pp.41-46 |
| SDM, ED | 2008-07-10 10:55 |
Hokkaido | Kaderu２・７ | Scalability of Vertical MOSFETs in Sub-10nm generation and its Mechanism Yuto Norifusa, Tetsuo Endoh (Tohoku Univ.) ED2008-60 SDM2008-79 |
In this paper, the device performances of sub-10nm Vertical MOSFETs are investigated. One of the drawbacks of convention... [more] | ED2008-60 SDM2008-79 pp.107-111 |
| VLD, ICD | 2008-03-06 16:35 |
Okinawa | TiRuRu | Comparison of Power consumption between dynamic voltage scheme and multi-supply voltage scheme for system LSI Satoshi Hanami, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-155 ICD2007-178 |
Reduction of power dissipation caused by dynamic current, gate leakage current, and subthreshold leakage current of mult... [more] | VLD2007-155 ICD2007-178 pp.67-72 |
| ICD, SIP, IE, IPSJ-SLDM | 2006-10-27 10:50 |
Miyagi | Design method of low-power dual-supply-voltage system LSI taking into account leakage current of MOSFET Shigeyoshi Watanabe, Masaki Kanai, Akira Nagasawa, Satoshi Hanami, Manabu Kobayashi, Toshinori Takabatake (SIT) |
Reduction of power dissipation caused by dynamic current, gate leakage current, and subthreshold leakage current of dual... [more] | SIP2006-106 ICD2006-132 IE2006-84 pp.31-36 |
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