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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, SDM, ITE-IST [detail] 2022-08-08
15:45		 Online   Evaluation of Low-Latency Cryptography MANTIS based Low-Power oriented Tamper-Resistant Circuit
Kosuke Hamaguchi, Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.) SDM2022-41 ICD2022-9		 Lightweight cryptography can not only be implemented in a small area, but also with low latency and low power consumptio... [more] SDM2022-41 ICD2022-9
pp.31-36
VLD, HWS [detail] 2022-03-08
13:00		 Online Online Implementation Evaluation of Glitch PUF Using a Low-Latency Cryptography MANTIS
Kosuke Hamaguchi, Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.) VLD2021-96 HWS2021-73		 This paper proposes a low-latency cipher MANTIS based PUF which uses signal glitch during encryption. The security level... [more] VLD2021-96 HWS2021-73
pp.111-116
HWS, VLD 2019-03-02
10:00		 Okinawa Okinawa Ken Seinen Kaikan An ultra-light weight implementation of PRINCE-family cryptographic processor
Kohei Matsuda, Makoto Nagata, Noriyuki Miura (Kobe Univ.) VLD2018-137 HWS2018-100		 An ultra-light-weight PRINCE cryptographic processor was proposed by Miura, et al. in 2017.
In this paper, based on thi... [more]		 VLD2018-137 HWS2018-100
pp.261-265
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