IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 11 of 11  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, RECONF, ICD, IPSJ-SLDM
(Joint) [detail]
2020-11-17
10:30
Online Online Power Analysis Based on Probability Calculation of Small Regions in LSI
Ryo Oba, Ryu Hoshino, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) VLD2020-13 ICD2020-33 DC2020-33 RECONF2020-32
Power consumption in LSI testing is higher than in functional mode since more switching activities occur. High power con... [more] VLD2020-13 ICD2020-33 DC2020-33 RECONF2020-32
pp.12-17
DC 2020-02-26
14:35
Tokyo   Power Analysis for Logic Area of LSI Including Memory Area
Yuya Kodama, Kohei Miyase, Daiki Takafuji, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2019-93
Power consumption during LSI testing is higher than functional mode. Excessive IR-drop causes excessive delay, resulting... [more] DC2019-93
pp.43-48
DC 2019-02-27
10:15
Tokyo Kikai-Shinko-Kaikan Bldg. Analysis of the hotspot distribution in the LSI
Yudai Kawano, Kohei Miyase (Kyutech), Shyue-Kung Lu (NTUST), Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2018-74
Performance degrading caused by high IR-drop in normal functional mode of LSI can be solved by improving power supply ne... [more] DC2018-74
pp.19-24
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-07
09:25
Kumamoto Kumamoto-Kenminkouryukan Parea On Avoiding Test Data Corruption by Optimal Scan Chain Grouping
Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara (KIT), Jun Qian (AMD) VLD2017-42 DC2017-48
Scan shift operations cause many gates to switch simultaneously. As a result, excessive IR-drop may occur, disrupting th... [more] VLD2017-42 DC2017-48
pp.91-94
DC 2016-02-17
10:25
Tokyo Kikai-Shinko-Kaikan Bldg. Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation
Fuqiang Li, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara (Kyutech) DC2015-87
Both logic paths and clock paths are subject to the impact of IR-Drop which occurs in capture mode during scan test. Thi... [more] DC2015-87
pp.7-12
DC 2014-06-20
14:05
Tokyo Kikai-Shinko-Kaikan Bldg. A X-Filling Method for Low-Capture-Power Scan Test Generation
Fuqiang Li, Xiaoqing Wen, Kohei Miyase, Stefan Holst, Seiji Kajihara (Kyushu Inst. of Tech.) DC2014-12
In order to generate a low capture power test pattern, we propose an
X-filling method to suppress local switching activ... [more]
DC2014-12
pp.15-20
DC 2012-06-22
16:10
Tokyo Room B3-1 Kikai-Shinko-Kaikan Bldg On Per-Cell Dynamic IR-Drop Estimation in At-Speed Scan Testing
Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue (NAIST) DC2012-15
It is well known that dynamic IR-drop analysis consumes large amount of time even for a few clock cycles. This paper add... [more] DC2012-15
pp.39-44
DC 2009-06-19
14:45
Tokyo Kikai-Shinko-Kaikan Bldg. Power & Noise Aware Test Utilizing Preliminary Estimation
Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo (STARC) DC2009-15
Advances in low power design technologies is making issues on power dissipation and IR-drop in testing more serious. Exc... [more] DC2009-15
pp.29-30
CAS, SIP, VLD 2007-06-22
10:50
Hokkaido Hokkaido Tokai Univ. (Sapporo) Timing error risk analysis and power grid optimization considering variabilities of manufacturing
Makoto Terao, Kenji Kusano, Yoshiyuki Kawakami, Masahiro Fukui (Ritsumeikan Univ.), Shuji Tsukiyama (Chuo Univ.) CAS2007-23 VLD2007-39 SIP2007-53
With the advent of super deep submicron age, the circuit behavior has large variation according to the process variation... [more] CAS2007-23 VLD2007-39 SIP2007-53
pp.25-30
ICD, SIP, IE, IPSJ-SLDM 2006-10-27
10:00
Miyagi   A multi objective optimization algorithm for power and ground routing
Kenji Kusano, Makoto Terao, Hironobu Ishijima, Yoshiyuki Kawakami, Masahiro Fukui (Ritsumeikan Univ.)
To the advent of super deep submicron age, power and ground routing becomes very important for the stable operation of t... [more] SIP2006-104 ICD2006-130 IE2006-82
pp.19-24
SIP, CAS, VLD 2006-06-22
15:50
Hokkaido Kitami Institute of Technology Sequence-Pair Based Compaction under Equi-Length Constraint
Takehiko Matsuo (Univ. of Kitakyushu), Keiji Kida (Jedat), Tetsuya Tashiro, Shigetoshi Nakatake (Univ. of Kitakyushu)
Equi-length constraints are widely used for a sub-stitution for IR-drop or skew constrains. This paper provides a linear... [more] CAS2006-6 VLD2006-19 SIP2006-29
pp.29-34
 Results 1 - 11 of 11  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan